Tegra194: drivers: SE and RNG1/PKA1 context save support

This patch adds the driver, to implement the programming sequence to
save/restore hardware context, during System Suspend/Resume.

Change-Id:

Tegra194: drivers: SE and RNG1/PKA1 context save support

This patch adds the driver, to implement the programming sequence to
save/restore hardware context, during System Suspend/Resume.

Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Jeff Tsai <jefft@nvidia.com>

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Tegra194: rename secure scratch register macros

This patch renames all the secure scratch registers to reflect
their usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV44_*

Tegra194: rename secure scratch register macros

This patch renames all the secure scratch registers to reflect
their usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_*

Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation

Rule 8.4, A compatible declaration shall be visible when an object
or function with external linkage is defined.

Add function delaration to the

Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation

Rule 8.4, A compatible declaration shall be visible when an object
or function with external linkage is defined.

Add function delaration to the header file.
Add suffix U to the unsigned constant define.

Change-Id: I54eba913a5fa38e4fdf3655931dc421d9510c691
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra194: mce: remove unsupported functionality

This patch cleans up the mce driver files to remove all the unsupported
functionality. The MCE/NVG interface is not restricted to the EL3 space,
so cl

Tegra194: mce: remove unsupported functionality

This patch cleans up the mce driver files to remove all the unsupported
functionality. The MCE/NVG interface is not restricted to the EL3 space,
so clients can issue commands to the MCE firmware directly.

Change-Id: Idcebc42f31805f9c1abe1c1edc17850151aca11d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: sanity check target cluster during core power on

This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported b

Tegra194: sanity check target cluster during core power on

This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported by the
platform.

Reported by: Rohit Khanna <rokhanna@nvidia.com>

Change-Id: I556ce17a58271cc119c86fae0a4d34267f08b338
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: fix defects flagged by MISRA scan

Main fixes:

Fix invalid use of function pointer [Rule 1.3]

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever o

Tegra194: fix defects flagged by MISRA scan

Main fixes:

Fix invalid use of function pointer [Rule 1.3]

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra194: mce: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Fix

Tegra194: mce: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Fix variable essential type doesn't match [Rule 10.3]

Added curly braces ({}) around if/while statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: Iaae2ecaba3caf1469c44910d4e6aed0661597a51
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra194: remove the GPU reset register macro

There is a possibility that once we have checked that the GPU is
in reset, some component can get still it out of reset.
This patch removes the check re

Tegra194: remove the GPU reset register macro

There is a possibility that once we have checked that the GPU is
in reset, some component can get still it out of reset.
This patch removes the check register macro.

Change-Id: Idbbba36f97e37c7db64ab9e42848a040ccd05acd
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: MC registers to allow CPU accesses to TZRAM

This patch adds MC registers and macros to allow CPU to access
TZRAM.

Change-Id: I46da526aa760c89714f8898591981bb6cfb29237
Signed-off-by: Varun

Tegra194: MC registers to allow CPU accesses to TZRAM

This patch adds MC registers and macros to allow CPU to access
TZRAM.

Change-Id: I46da526aa760c89714f8898591981bb6cfb29237
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: increase MAX_MMAP_REGIONS macro value

This patch increases the MAX_MMAP_REGIONS value to 30 from 25 to
allow addition of more MMU mappings.

Change-Id: I5c758c432f5cc77299608e25ba2fd92c382

Tegra194: increase MAX_MMAP_REGIONS macro value

This patch increases the MAX_MMAP_REGIONS value to 30 from 25 to
allow addition of more MMU mappings.

Change-Id: I5c758c432f5cc77299608e25ba2fd92c3822379d
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: update nvg header to v6.1

This patch updates t194_nvg.h to v6.1 and does not issue NVG
commands for unsupported platforms.

Change-Id: I506b594a70a3651d01a412ab79b3c8919b1d66f1
Signed-off-

Tegra194: update nvg header to v6.1

This patch updates t194_nvg.h to v6.1 and does not issue NVG
commands for unsupported platforms.

Change-Id: I506b594a70a3651d01a412ab79b3c8919b1d66f1
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: update cache operations supported by the ROC

This patch updates the cache ops to use system registers in
order to trigger cache flush/clean operations.

Change-Id: I888abad22f22b8a33c7193b

Tegra194: update cache operations supported by the ROC

This patch updates the cache ops to use system registers in
order to trigger cache flush/clean operations.

Change-Id: I888abad22f22b8a33c7193b991fad8c4a78030d0
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: memctrl: platform handlers to reprogram MSS

Introduce platform handlers to reprogram the MSS settings.

Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861
Signed-off-by: Puneet Saxena <p

Tegra194: memctrl: platform handlers to reprogram MSS

Introduce platform handlers to reprogram the MSS settings.

Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: core and cluster count values

This patch updates the total number of CPU clusters and number
of cores per cluster, in the platform makefile.

Change-Id: I569ebc1bb794ecab09a1043511b3d936bf

Tegra194: core and cluster count values

This patch updates the total number of CPU clusters and number
of cores per cluster, in the platform makefile.

Change-Id: I569ebc1bb794ecab09a1043511b3d936bf450428
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: correct the TEGRA_CAR_RESET_BASE macro value

This patch corrects the TEGRA_CAR_RESET_BASE macro value to
0x20000000 from 0x200000000.

Change-Id: Iba25394ea99237df85395c39059926c5a8b26a84

Tegra194: correct the TEGRA_CAR_RESET_BASE macro value

This patch corrects the TEGRA_CAR_RESET_BASE macro value to
0x20000000 from 0x200000000.

Change-Id: Iba25394ea99237df85395c39059926c5a8b26a84
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: add MC_SECURITY mask defines

This patch adds masks for the TZDRAM base/size registers.

Change-Id: I5f688793be8cace28d2aa2d177a295e4faffd666
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

Tegra194: Update wake mask, wake time for cpu offlining

This patch updates the wake mask and wake time to indicate to the
mce/mts that the cpu is powering down. Wake time is set to highest
possible

Tegra194: Update wake mask, wake time for cpu offlining

This patch updates the wake mask and wake time to indicate to the
mce/mts that the cpu is powering down. Wake time is set to highest
possible value and wake mask is set to zero.

Change-Id: Ic5abf15e7b98f911def6aa610d300b0668cd287e
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>

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Tegra194: program stream ids for XUSB

T194 XUSB has support for XUSB virtualization. It will have one
physical function (PF) and four Virtual function (VF)

There were below two SIDs for XUSB until

Tegra194: program stream ids for XUSB

T194 XUSB has support for XUSB virtualization. It will have one
physical function (PF) and four Virtual function (VF)

There were below two SIDs for XUSB until T186.
1) #define TEGRA_SID_XUSB_HOST 0x1bU
2) #define TEGRA_SID_XUSB_DEV 0x1cU

We have below four new SIDs added for VF(s)
3) #define TEGRA_SID_XUSB_VF0 0x5dU
4) #define TEGRA_SID_XUSB_VF1 0x5eU
5) #define TEGRA_SID_XUSB_VF2 0x5fU
6) #define TEGRA_SID_XUSB_VF3 0x60U

When virtualization is enabled then we have to disable SID override
and program above SIDs in below newly added SID registers in XUSB
PADCTL MMIO space. These registers are TZ protected and so need to
be done in ATF.
a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)

This change disables SID override and programs XUSB SIDs in
above registers to support both virtualization and non-virtualization.

Change-Id: I38213a72999e933c44c5392441f91034d3b47a39
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>

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Tegra194: Update checks for c-state stats

This patch adds proper checks for the cpu c-stats. It checks both
cpu id and stat id before sending the nvg request to ccplex.

Change-Id: I732957d1e10d6ce6

Tegra194: Update checks for c-state stats

This patch adds proper checks for the cpu c-stats. It checks both
cpu id and stat id before sending the nvg request to ccplex.

Change-Id: I732957d1e10d6ce6cffb2c6f5963ca614aadd948
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>

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Tegra194: smmu: fix mask for board revision id

Need to use bitwise & instead of condition &&.

Change-Id: I8f70aac95d116188ba972f3d38b02e1d3dd32acb
Signed-off-by: Pritesh Raithatha <praithatha@nvidi

Tegra194: smmu: fix mask for board revision id

Need to use bitwise & instead of condition &&.

Change-Id: I8f70aac95d116188ba972f3d38b02e1d3dd32acb
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: smmu: ISO support

The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not

Tegra194: smmu: ISO support

The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.

Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: Initialize smmu on system suspend exit

System suspend sequence involves initializing the SMMU
as a part of the system suspend exit, which is currently
not present for Tegra194 platform.

T

Tegra194: Initialize smmu on system suspend exit

System suspend sequence involves initializing the SMMU
as a part of the system suspend exit, which is currently
not present for Tegra194 platform.

Thus call tegra_smmu_init() as a part of system suspend
exit.

Change-Id: I3086301743019e05a40fd221372e7f8713f286ae
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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Tegra194: Update cpu core-id calculation

This patch updates the cpu core id calculation to match with
internal numbering method used by the MTS.

Change-Id: I5fbe9c8685c23017edc796e114d07c5e979e0d3d

Tegra194: Update cpu core-id calculation

This patch updates the cpu core id calculation to match with
internal numbering method used by the MTS.

Change-Id: I5fbe9c8685c23017edc796e114d07c5e979e0d3d
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>

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Tegra194: read-modify-write ACTLR_ELx registers

This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.

Change-Id: I536dce75c01356ce054dd2edee80875e56164439
Signed

Tegra194: read-modify-write ACTLR_ELx registers

This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.

Change-Id: I536dce75c01356ce054dd2edee80875e56164439
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra194: Enable fake system suspend

Fake system suspend for Tegra194, calls the routine
tegra_secure_entrypoint() instead of calling WFI.
In essence, this is a debug mode that ensures
that the code

Tegra194: Enable fake system suspend

Fake system suspend for Tegra194, calls the routine
tegra_secure_entrypoint() instead of calling WFI.
In essence, this is a debug mode that ensures
that the code path of kernel->ATF and back to kernel
is executed without depending on other components
involved in the system suspend path.

This is for ensuring that verification of system suspend
can be done on pre-silicon platforms without depending on
the rest of the layers being enabled.

Change-Id: I18572b169b7ef786f9029600dad9ef5728634f2b
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

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