1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <common/interrupt_props.h> 13 #include <common/tbbr/tbbr_img_def.h> 14 #include <plat/common/common_def.h> 15 16 #define PLAT_SOCFPGA_STRATIX10 1 17 #define PLAT_SOCFPGA_AGILEX 2 18 19 #define PLAT_CPUID_RELEASE 0xffe1b000 20 #define PLAT_SEC_ENTRY 0xffe1b008 21 22 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 23 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 24 25 /* Define next boot image name and offset */ 26 #define PLAT_NS_IMAGE_OFFSET 0x50000 27 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 28 29 /******************************************************************************* 30 * Platform binary types for linking 31 ******************************************************************************/ 32 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 33 #define PLATFORM_LINKER_ARCH aarch64 34 35 /* SoCFPGA supports up to 124GB RAM */ 36 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 37 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 38 39 40 /******************************************************************************* 41 * Generic platform constants 42 ******************************************************************************/ 43 #define PLAT_PRIMARY_CPU 0 44 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 45 46 /* Size of cacheable stacks */ 47 #define PLATFORM_STACK_SIZE 0x2000 48 49 /* PSCI related constant */ 50 #define PLAT_NUM_POWER_DOMAINS 5 51 #define PLAT_MAX_PWR_LVL 1 52 #define PLAT_MAX_RET_STATE 1 53 #define PLAT_MAX_OFF_STATE 2 54 #define PLATFORM_SYSTEM_COUNT 1 55 #define PLATFORM_CLUSTER_COUNT 1 56 #define PLATFORM_CLUSTER0_CORE_COUNT 4 57 #define PLATFORM_CLUSTER1_CORE_COUNT 0 58 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 59 PLATFORM_CLUSTER0_CORE_COUNT) 60 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 61 62 /* Interrupt related constant */ 63 64 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 65 66 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 67 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 68 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 69 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 70 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 71 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 72 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 73 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 74 75 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 76 #define TSP_SEC_MEM_BASE BL32_BASE 77 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 78 /******************************************************************************* 79 * Platform memory map related constants 80 ******************************************************************************/ 81 #define DRAM_BASE (0x0) 82 #define DRAM_SIZE (0x80000000) 83 84 #define OCRAM_BASE (0xFFE00000) 85 #define OCRAM_SIZE (0x00040000) 86 87 #define MEM64_BASE (0x0100000000) 88 #define MEM64_SIZE (0x1F00000000) 89 90 #define DEVICE1_BASE (0x80000000) 91 #define DEVICE1_SIZE (0x60000000) 92 93 #define DEVICE2_BASE (0xF7000000) 94 #define DEVICE2_SIZE (0x08E00000) 95 96 #define DEVICE3_BASE (0xFFFC0000) 97 #define DEVICE3_SIZE (0x00008000) 98 99 #define DEVICE4_BASE (0x2000000000) 100 #define DEVICE4_SIZE (0x0100000000) 101 102 /******************************************************************************* 103 * BL31 specific defines. 104 ******************************************************************************/ 105 /* 106 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 107 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 108 * little space for growth. 109 */ 110 111 112 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 113 114 #define BL1_RO_BASE (0xffe00000) 115 #define BL1_RO_LIMIT (0xffe0f000) 116 #define BL1_RW_BASE (0xffe10000) 117 #define BL1_RW_LIMIT (0xffe1ffff) 118 #define BL1_RW_SIZE (0x14000) 119 120 #define BL2_BASE (0xffe00000) 121 #define BL2_LIMIT (0xffe1b000) 122 123 #define BL31_BASE (0xffe1c000) 124 #define BL31_LIMIT (0xffe3bfff) 125 126 /******************************************************************************* 127 * Platform specific page table and MMU setup constants 128 ******************************************************************************/ 129 #define MAX_XLAT_TABLES 8 130 #define MAX_MMAP_REGIONS 16 131 132 /******************************************************************************* 133 * Declarations and constants to access the mailboxes safely. Each mailbox is 134 * aligned on the biggest cache line size in the platform. This is known only 135 * to the platform as it might have a combination of integrated and external 136 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 137 * line at any cache level. They could belong to different cpus/clusters & 138 * get written while being protected by different locks causing corruption of 139 * a valid mailbox address. 140 ******************************************************************************/ 141 #define CACHE_WRITEBACK_SHIFT 6 142 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 143 144 #define PLAT_GIC_BASE (0xFFFC0000) 145 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 146 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 147 #define PLAT_GICR_BASE 0 148 149 /******************************************************************************* 150 * UART related constants 151 ******************************************************************************/ 152 #define PLAT_UART0_BASE (0xFFC02000) 153 #define PLAT_UART1_BASE (0xFFC02100) 154 155 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 156 157 #define PLAT_BAUDRATE (115200) 158 #define PLAT_UART_CLOCK (100000000) 159 160 /******************************************************************************* 161 * System counter frequency related constants 162 ******************************************************************************/ 163 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 164 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400) 165 166 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 167 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 168 169 /* 170 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 171 * terminology. On a GICv2 system or mode, the lists will be merged and treated 172 * as Group 0 interrupts. 173 */ 174 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 175 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 176 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 177 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 178 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 179 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 180 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 181 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 182 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 183 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 184 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 185 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 186 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 187 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 188 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 189 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 190 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 191 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 192 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 193 194 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 195 196 #define MAX_IO_HANDLES 4 197 #define MAX_IO_DEVICES 4 198 #define MAX_IO_BLOCK_DEVICES 2 199 200 #endif /* PLATFORM_DEF_H */ 201 202