zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node

Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value t

zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node

Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b

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zynqmp: pm: clock: Move custom flags to typeflags

Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.

Signed-off-by: Rajan Va

zynqmp: pm: clock: Move custom flags to typeflags

Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78

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zynqmp: pm: clock: Add support for custom type flags

Add support to add extra custom type flags and provide
to caller in topology query.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off

zynqmp: pm: clock: Add support for custom type flags

Add support to add extra custom type flags and provide
to caller in topology query.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40

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plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function

Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.

Signed-off-by: Rajan Vaja <rajan.vaja@xili

plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function

Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81

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Merge changes from topic "sip-svc" into integration

* changes:
intel: Implement platform specific system reset 2
intel: Enable SiP SMC secure register access

Merge "uniphier: call uniphier_scp_is_running() only when on-chip STM is supported" into integration

Merge "intel: Fix memory calibration" into integration

Merge "plat: rpi4: Skip UART initialisation" into integration

Merge changes from topic "add-versal-soc-support" into integration

* changes:
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
zynqmp: pm: Fix clock models and IDs of GEM-related clocks

Merge changes from topic "add-versal-soc-support" into integration

* changes:
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
zynqmp: pm: Fix clock models and IDs of GEM-related clocks
zynqmp: pm: Rename FPD WDT clock ID
plat: xilinx: zynqmp: Correct syscnt freq for QEMU
arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
arm64: zynqmp: Add id for new RFSoC device ZU39DR

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Merge "allwinner: Move the NOBITS region to SRAM A1" into integration

Merge "intel: Remove un-needed checks for qspi driver r/w" into integration

intel: Remove un-needed checks for qspi driver r/w

This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.

Signed-off-by: Hadi Asyrafi

intel: Remove un-needed checks for qspi driver r/w

This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53

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Tegra194: drivers: fix violations of MISRA Rule 21.1

This patch fixes the violations of Rule 21.1 from all the
header files.

Rule 21.1 "#define and #undef shall not be used on a reserved

Tegra194: drivers: fix violations of MISRA Rule 21.1

This patch fixes the violations of Rule 21.1 from all the
header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc

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Tegra: include: fix violations of MISRA Rule 21.1

This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.

Rule 21.1 "#define and #undef shall not be used on a reserved

Tegra: include: fix violations of MISRA Rule 21.1

This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185

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Merge "Unify type of "cpu_idx" across PSCI module." into integration

Unify type of "cpu_idx" across PSCI module.

NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned i

Unify type of "cpu_idx" across PSCI module.

NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned int" type.

Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.

2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent

Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.

Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c

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Merge "rcar_gen3: plat: Pass DT to OpTee OS" into integration

Merge "plat: nvidia: remove spurious UTF-8 characters at top of platform files" into integration

Merge "FVP: Remove re-definition of topology related build options" into integration

Merge "FVP: Stop reclaiming init code with Clang builds" into integration

Merge "rcar_gen3: drivers: ddr: Move DDR drivers out of staging" into integration

FVP: Remove re-definition of topology related build options

This patch removes re-definition of the following FVP build
options from plat\arm\board\fvp\fvp_def.h:
'FVP_CLUSTER_COUNT'
'FVP_MAX_CPUS

FVP: Remove re-definition of topology related build options

This patch removes re-definition of the following FVP build
options from plat\arm\board\fvp\fvp_def.h:
'FVP_CLUSTER_COUNT'
'FVP_MAX_CPUS_PER_CLUSTER'
'FVP_MAX_PE_PER_CPU'
which are set in platform.mk.

This fixes a potential problem when a build option set in
platform.mk file can be re-defined in fvp_def.h header file
used by other build component with a different makefile which
does not set this option.
Ref. GENFW-3505.

Change-Id: I4288629920516acf2c239c7b733f92a0c5a812ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge "Simplify PMF helper macro definitions across header files" into integration

Merge "Remove redundant declarations." into integration

plat: nvidia: remove spurious UTF-8 characters at top of platform files

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423