1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/io/io_block.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_dummy.h> 17 #include <drivers/io/io_mtd.h> 18 #include <drivers/io/io_storage.h> 19 #include <drivers/mmc.h> 20 #include <drivers/partition/partition.h> 21 #include <drivers/raw_nand.h> 22 #include <drivers/spi_nand.h> 23 #include <drivers/st/io_mmc.h> 24 #include <drivers/st/io_stm32image.h> 25 #include <drivers/st/stm32_fmc2_nand.h> 26 #include <drivers/st/stm32_qspi.h> 27 #include <drivers/st/stm32_sdmmc2.h> 28 #include <lib/mmio.h> 29 #include <lib/utils.h> 30 #include <plat/common/platform.h> 31 32 /* IO devices */ 33 static const io_dev_connector_t *dummy_dev_con; 34 static uintptr_t dummy_dev_handle; 35 static uintptr_t dummy_dev_spec; 36 37 static uintptr_t image_dev_handle; 38 static uintptr_t storage_dev_handle; 39 40 #if STM32MP_SDMMC || STM32MP_EMMC 41 static io_block_spec_t gpt_block_spec = { 42 .offset = 0, 43 .length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */ 44 }; 45 46 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 47 48 static const io_block_dev_spec_t mmc_block_dev_spec = { 49 /* It's used as temp buffer in block driver */ 50 .buffer = { 51 .offset = (size_t)&block_buffer, 52 .length = MMC_BLOCK_SIZE, 53 }, 54 .ops = { 55 .read = mmc_read_blocks, 56 .write = NULL, 57 }, 58 .block_size = MMC_BLOCK_SIZE, 59 }; 60 61 static const io_dev_connector_t *mmc_dev_con; 62 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 63 64 #if STM32MP_RAW_NAND 65 static io_mtd_dev_spec_t nand_dev_spec = { 66 .ops = { 67 .init = nand_raw_init, 68 .read = nand_read, 69 }, 70 }; 71 72 static const io_dev_connector_t *nand_dev_con; 73 #endif 74 75 #if STM32MP_SPI_NAND 76 static io_mtd_dev_spec_t spi_nand_dev_spec = { 77 .ops = { 78 .init = spi_nand_init, 79 .read = nand_read, 80 }, 81 }; 82 83 static const io_dev_connector_t *spi_dev_con; 84 #endif 85 86 #ifdef AARCH32_SP_OPTEE 87 static const struct stm32image_part_info optee_header_partition_spec = { 88 .name = OPTEE_HEADER_IMAGE_NAME, 89 .binary_type = OPTEE_HEADER_BINARY_TYPE, 90 }; 91 92 static const struct stm32image_part_info optee_pager_partition_spec = { 93 .name = OPTEE_PAGER_IMAGE_NAME, 94 .binary_type = OPTEE_PAGER_BINARY_TYPE, 95 }; 96 97 static const struct stm32image_part_info optee_paged_partition_spec = { 98 .name = OPTEE_PAGED_IMAGE_NAME, 99 .binary_type = OPTEE_PAGED_BINARY_TYPE, 100 }; 101 #else 102 static const io_block_spec_t bl32_block_spec = { 103 .offset = BL32_BASE, 104 .length = STM32MP_BL32_SIZE 105 }; 106 #endif 107 108 static const io_block_spec_t bl2_block_spec = { 109 .offset = BL2_BASE, 110 .length = STM32MP_BL2_SIZE, 111 }; 112 113 static const struct stm32image_part_info bl33_partition_spec = { 114 .name = BL33_IMAGE_NAME, 115 .binary_type = BL33_BINARY_TYPE, 116 }; 117 118 enum { 119 IMG_IDX_BL33, 120 #ifdef AARCH32_SP_OPTEE 121 IMG_IDX_OPTEE_HEADER, 122 IMG_IDX_OPTEE_PAGER, 123 IMG_IDX_OPTEE_PAGED, 124 #endif 125 IMG_IDX_NUM 126 }; 127 128 static struct stm32image_device_info stm32image_dev_info_spec __unused = { 129 .lba_size = MMC_BLOCK_SIZE, 130 .part_info[IMG_IDX_BL33] = { 131 .name = BL33_IMAGE_NAME, 132 .binary_type = BL33_BINARY_TYPE, 133 }, 134 #ifdef AARCH32_SP_OPTEE 135 .part_info[IMG_IDX_OPTEE_HEADER] = { 136 .name = OPTEE_HEADER_IMAGE_NAME, 137 .binary_type = OPTEE_HEADER_BINARY_TYPE, 138 }, 139 .part_info[IMG_IDX_OPTEE_PAGER] = { 140 .name = OPTEE_PAGER_IMAGE_NAME, 141 .binary_type = OPTEE_PAGER_BINARY_TYPE, 142 }, 143 .part_info[IMG_IDX_OPTEE_PAGED] = { 144 .name = OPTEE_PAGED_IMAGE_NAME, 145 .binary_type = OPTEE_PAGED_BINARY_TYPE, 146 }, 147 #endif 148 }; 149 150 static io_block_spec_t stm32image_block_spec = { 151 .offset = 0, 152 .length = 0, 153 }; 154 155 static const io_dev_connector_t *stm32image_dev_con __unused; 156 157 static int open_dummy(const uintptr_t spec); 158 static int open_image(const uintptr_t spec); 159 static int open_storage(const uintptr_t spec); 160 161 struct plat_io_policy { 162 uintptr_t *dev_handle; 163 uintptr_t image_spec; 164 int (*check)(const uintptr_t spec); 165 }; 166 167 static const struct plat_io_policy policies[] = { 168 [BL2_IMAGE_ID] = { 169 .dev_handle = &dummy_dev_handle, 170 .image_spec = (uintptr_t)&bl2_block_spec, 171 .check = open_dummy 172 }, 173 #ifdef AARCH32_SP_OPTEE 174 [BL32_IMAGE_ID] = { 175 .dev_handle = &image_dev_handle, 176 .image_spec = (uintptr_t)&optee_header_partition_spec, 177 .check = open_image 178 }, 179 [BL32_EXTRA1_IMAGE_ID] = { 180 .dev_handle = &image_dev_handle, 181 .image_spec = (uintptr_t)&optee_pager_partition_spec, 182 .check = open_image 183 }, 184 [BL32_EXTRA2_IMAGE_ID] = { 185 .dev_handle = &image_dev_handle, 186 .image_spec = (uintptr_t)&optee_paged_partition_spec, 187 .check = open_image 188 }, 189 #else 190 [BL32_IMAGE_ID] = { 191 .dev_handle = &dummy_dev_handle, 192 .image_spec = (uintptr_t)&bl32_block_spec, 193 .check = open_dummy 194 }, 195 #endif 196 [BL33_IMAGE_ID] = { 197 .dev_handle = &image_dev_handle, 198 .image_spec = (uintptr_t)&bl33_partition_spec, 199 .check = open_image 200 }, 201 #if STM32MP_SDMMC || STM32MP_EMMC 202 [GPT_IMAGE_ID] = { 203 .dev_handle = &storage_dev_handle, 204 .image_spec = (uintptr_t)&gpt_block_spec, 205 .check = open_storage 206 }, 207 #endif 208 [STM32_IMAGE_ID] = { 209 .dev_handle = &storage_dev_handle, 210 .image_spec = (uintptr_t)&stm32image_block_spec, 211 .check = open_storage 212 } 213 }; 214 215 static int open_dummy(const uintptr_t spec) 216 { 217 return io_dev_init(dummy_dev_handle, 0); 218 } 219 220 static int open_image(const uintptr_t spec) 221 { 222 return io_dev_init(image_dev_handle, 0); 223 } 224 225 static int open_storage(const uintptr_t spec) 226 { 227 return io_dev_init(storage_dev_handle, 0); 228 } 229 230 static void print_boot_device(boot_api_context_t *boot_context) 231 { 232 switch (boot_context->boot_interface_selected) { 233 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 234 INFO("Using SDMMC\n"); 235 break; 236 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 237 INFO("Using EMMC\n"); 238 break; 239 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 240 INFO("Using FMC NAND\n"); 241 break; 242 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 243 INFO("Using SPI NAND\n"); 244 break; 245 default: 246 ERROR("Boot interface not found\n"); 247 panic(); 248 break; 249 } 250 251 if (boot_context->boot_interface_instance != 0U) { 252 INFO(" Instance %d\n", boot_context->boot_interface_instance); 253 } 254 } 255 256 #if STM32MP_SDMMC || STM32MP_EMMC 257 static void boot_mmc(enum mmc_device_type mmc_dev_type, 258 uint16_t boot_interface_instance) 259 { 260 int io_result __unused; 261 uint8_t idx; 262 struct stm32image_part_info *part; 263 struct stm32_sdmmc2_params params; 264 struct mmc_device_info device_info; 265 const partition_entry_t *entry; 266 267 zeromem(&device_info, sizeof(struct mmc_device_info)); 268 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 269 270 device_info.mmc_dev_type = mmc_dev_type; 271 272 switch (boot_interface_instance) { 273 case 1: 274 params.reg_base = STM32MP_SDMMC1_BASE; 275 break; 276 case 2: 277 params.reg_base = STM32MP_SDMMC2_BASE; 278 break; 279 case 3: 280 params.reg_base = STM32MP_SDMMC3_BASE; 281 break; 282 default: 283 WARN("SDMMC instance not found, using default\n"); 284 if (mmc_dev_type == MMC_IS_SD) { 285 params.reg_base = STM32MP_SDMMC1_BASE; 286 } else { 287 params.reg_base = STM32MP_SDMMC2_BASE; 288 } 289 break; 290 } 291 292 params.device_info = &device_info; 293 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 294 ERROR("SDMMC%u init failed\n", boot_interface_instance); 295 panic(); 296 } 297 298 /* Open MMC as a block device to read GPT table */ 299 io_result = register_io_dev_block(&mmc_dev_con); 300 if (io_result != 0) { 301 panic(); 302 } 303 304 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 305 &storage_dev_handle); 306 assert(io_result == 0); 307 308 partition_init(GPT_IMAGE_ID); 309 310 io_result = io_dev_close(storage_dev_handle); 311 assert(io_result == 0); 312 313 stm32image_dev_info_spec.device_size = 314 stm32_sdmmc2_mmc_get_device_size(); 315 316 for (idx = 0U; idx < IMG_IDX_NUM; idx++) { 317 part = &stm32image_dev_info_spec.part_info[idx]; 318 entry = get_partition_entry(part->name); 319 if (entry == NULL) { 320 ERROR("Partition %s not found\n", part->name); 321 panic(); 322 } 323 324 part->part_offset = entry->start; 325 part->bkp_offset = 0U; 326 } 327 328 /* 329 * Re-open MMC with io_mmc, for better perfs compared to 330 * io_block. 331 */ 332 io_result = register_io_dev_mmc(&mmc_dev_con); 333 assert(io_result == 0); 334 335 io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle); 336 assert(io_result == 0); 337 338 io_result = register_io_dev_stm32image(&stm32image_dev_con); 339 assert(io_result == 0); 340 341 io_result = io_dev_open(stm32image_dev_con, 342 (uintptr_t)&stm32image_dev_info_spec, 343 &image_dev_handle); 344 assert(io_result == 0); 345 } 346 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 347 348 #if STM32MP_RAW_NAND 349 static void boot_fmc2_nand(boot_api_context_t *boot_context) 350 { 351 int io_result __unused; 352 uint8_t idx; 353 struct stm32image_part_info *part; 354 355 io_result = stm32_fmc2_init(); 356 assert(io_result == 0); 357 358 /* Register the IO device on this platform */ 359 io_result = register_io_dev_mtd(&nand_dev_con); 360 assert(io_result == 0); 361 362 /* Open connections to device */ 363 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 364 &storage_dev_handle); 365 assert(io_result == 0); 366 367 stm32image_dev_info_spec.device_size = nand_dev_spec.device_size; 368 369 idx = IMG_IDX_BL33; 370 part = &stm32image_dev_info_spec.part_info[idx]; 371 part->part_offset = STM32MP_NAND_BL33_OFFSET; 372 part->bkp_offset = nand_dev_spec.erase_size; 373 374 #ifdef AARCH32_SP_OPTEE 375 idx = IMG_IDX_OPTEE_HEADER; 376 part = &stm32image_dev_info_spec.part_info[idx]; 377 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 378 part->bkp_offset = nand_dev_spec.erase_size; 379 380 idx = IMG_IDX_OPTEE_PAGED; 381 part = &stm32image_dev_info_spec.part_info[idx]; 382 part->part_offset = STM32MP_NAND_TEED_OFFSET; 383 part->bkp_offset = nand_dev_spec.erase_size; 384 385 idx = IMG_IDX_OPTEE_PAGER; 386 part = &stm32image_dev_info_spec.part_info[idx]; 387 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 388 part->bkp_offset = nand_dev_spec.erase_size; 389 #endif 390 391 io_result = register_io_dev_stm32image(&stm32image_dev_con); 392 assert(io_result == 0); 393 394 io_result = io_dev_open(stm32image_dev_con, 395 (uintptr_t)&stm32image_dev_info_spec, 396 &image_dev_handle); 397 assert(io_result == 0); 398 } 399 #endif /* STM32MP_RAW_NAND */ 400 401 #if STM32MP_SPI_NAND 402 static void boot_spi_nand(boot_api_context_t *boot_context) 403 { 404 int io_result __unused; 405 uint8_t idx; 406 struct stm32image_part_info *part; 407 408 io_result = stm32_qspi_init(); 409 assert(io_result == 0); 410 411 io_result = register_io_dev_mtd(&spi_dev_con); 412 assert(io_result == 0); 413 414 /* Open connections to device */ 415 io_result = io_dev_open(spi_dev_con, 416 (uintptr_t)&spi_nand_dev_spec, 417 &storage_dev_handle); 418 assert(io_result == 0); 419 420 stm32image_dev_info_spec.device_size = 421 spi_nand_dev_spec.device_size; 422 423 idx = IMG_IDX_BL33; 424 part = &stm32image_dev_info_spec.part_info[idx]; 425 part->part_offset = STM32MP_NAND_BL33_OFFSET; 426 part->bkp_offset = spi_nand_dev_spec.erase_size; 427 428 #ifdef AARCH32_SP_OPTEE 429 idx = IMG_IDX_OPTEE_HEADER; 430 part = &stm32image_dev_info_spec.part_info[idx]; 431 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 432 part->bkp_offset = spi_nand_dev_spec.erase_size; 433 434 idx = IMG_IDX_OPTEE_PAGED; 435 part = &stm32image_dev_info_spec.part_info[idx]; 436 part->part_offset = STM32MP_NAND_TEED_OFFSET; 437 part->bkp_offset = spi_nand_dev_spec.erase_size; 438 439 idx = IMG_IDX_OPTEE_PAGER; 440 part = &stm32image_dev_info_spec.part_info[idx]; 441 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 442 part->bkp_offset = spi_nand_dev_spec.erase_size; 443 #endif 444 445 io_result = register_io_dev_stm32image(&stm32image_dev_con); 446 assert(io_result == 0); 447 448 io_result = io_dev_open(stm32image_dev_con, 449 (uintptr_t)&stm32image_dev_info_spec, 450 &image_dev_handle); 451 assert(io_result == 0); 452 } 453 #endif /* STM32MP_SPI_NAND */ 454 455 void stm32mp_io_setup(void) 456 { 457 int io_result __unused; 458 boot_api_context_t *boot_context = 459 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 460 461 print_boot_device(boot_context); 462 463 if ((boot_context->boot_partition_used_toboot == 1U) || 464 (boot_context->boot_partition_used_toboot == 2U)) { 465 INFO("Boot used partition fsbl%d\n", 466 boot_context->boot_partition_used_toboot); 467 } 468 469 io_result = register_io_dev_dummy(&dummy_dev_con); 470 assert(io_result == 0); 471 472 io_result = io_dev_open(dummy_dev_con, dummy_dev_spec, 473 &dummy_dev_handle); 474 assert(io_result == 0); 475 476 switch (boot_context->boot_interface_selected) { 477 #if STM32MP_SDMMC 478 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 479 dmbsy(); 480 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 481 break; 482 #endif 483 #if STM32MP_EMMC 484 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 485 dmbsy(); 486 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 487 break; 488 #endif 489 #if STM32MP_RAW_NAND 490 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 491 dmbsy(); 492 boot_fmc2_nand(boot_context); 493 break; 494 #endif 495 #if STM32MP_SPI_NAND 496 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 497 dmbsy(); 498 boot_spi_nand(boot_context); 499 break; 500 #endif 501 502 default: 503 ERROR("Boot interface %d not supported\n", 504 boot_context->boot_interface_selected); 505 break; 506 } 507 } 508 509 /* 510 * Return an IO device handle and specification which can be used to access 511 * an image. Use this to enforce platform load policy. 512 */ 513 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 514 uintptr_t *image_spec) 515 { 516 int rc; 517 const struct plat_io_policy *policy; 518 519 assert(image_id < ARRAY_SIZE(policies)); 520 521 policy = &policies[image_id]; 522 rc = policy->check(policy->image_spec); 523 if (rc == 0) { 524 *image_spec = policy->image_spec; 525 *dev_handle = *(policy->dev_handle); 526 } 527 528 return rc; 529 } 530