Tegra: gicv2: initialize target masks

This patch initializes the target masks in the GICv2 driver
data, for all PEs. This will allow platforms to set the PE
target for SPIs.

Change-Id: I7bf2ad79c04

Tegra: gicv2: initialize target masks

This patch initializes the target masks in the GICv2 driver
data, for all PEs. This will allow platforms to set the PE
target for SPIs.

Change-Id: I7bf2ad79c04c2555ab310acba17823fb157327a3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: trigger CPU0 hotplug power on using FC

Hotplug poweron is not working for boot CPU as it's being
triggerred using PMC and not with Flow Controller. This is
happening because "cpu_powergate

Tegra210: trigger CPU0 hotplug power on using FC

Hotplug poweron is not working for boot CPU as it's being
triggerred using PMC and not with Flow Controller. This is
happening because "cpu_powergate_mask" is only getting set
for non-boot CPU's as the boot CPU's first bootup follows
different code path. The patch is marking a CPU as ON within
"cpu_powergate_mask" when turning its power domain on
during power on. This will ensure only first bootup on all
CPU's is using PMC and subsequent hotplug poweron will be
using Flow Controller.

Change-Id: Ie9e86e6f9a777d41508a93d2ce286f31307932c2
Signed-off-by: sumitg <sumitg@nvidia.com>

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Tegra: memctrl: cleanup streamid override registers

Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of t

Tegra: memctrl: cleanup streamid override registers

Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of the client so need to remove register list and do not
set streamid_override_cfg.

Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC
bypass as of now. Will revisit once these issues are fixed.

Change-Id: I3f67e2a0e1b53160e2218f3acace7da45532f934
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra: memctrl_v2: remove support to secure TZSRAM

This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.

Tegra: memctrl_v2: remove support to secure TZSRAM

This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.

Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: include platform headers from individual makefiles

This patch modifies PLAT_INCLUDES to include individual Tegra SoC
headers from the platform's makefile.

Change-Id: If5248667f4e58ac18727d37

Tegra: include platform headers from individual makefiles

This patch modifies PLAT_INCLUDES to include individual Tegra SoC
headers from the platform's makefile.

Change-Id: If5248667f4e58ac18727d37a18fbba8e53f2d7b5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro

This patch renames 'ENABLE_WDT_LEGACY_FIQ_HANDLING' macro to
'ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING', to indicate that this
is a Tegra feature.

Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro

This patch renames 'ENABLE_WDT_LEGACY_FIQ_HANDLING' macro to
'ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING', to indicate that this
is a Tegra feature.

Change-Id: I5c4431e662223ee80efbfd5ec2513f8b1cadfc50
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: SiP function ID to read SMMU_PER registers

This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER
error records from all supported SMMU blocks.

The register values are passed

Tegra194: SiP function ID to read SMMU_PER registers

This patch introduces SiP function ID, 0xC200FF00, to read SMMU_PER
error records from all supported SMMU blocks.

The register values are passed over to the client via CPU registers
X1 - X3, where

X1 = SMMU_PER[instance #1] | SMMU_PER[instance #0]
X2 = SMMU_PER[instance #3] | SMMU_PER[instance #2]
X3 = SMMU_PER[instance #5] | SMMU_PER[instance #4]

Change-Id: Id56263f558838ad05f6021f8432e618e99e190fc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl: map video memory as uncached

Memmap video memory as uncached normal memory by adding flag
'MT_NON_CACHEABLE' in mmap_add_dynamic_region().
This improves the time taken for clearing t

Tegra: memctrl: map video memory as uncached

Memmap video memory as uncached normal memory by adding flag
'MT_NON_CACHEABLE' in mmap_add_dynamic_region().
This improves the time taken for clearing the non-overlapping video
memory:

test conditions: 32MB memory size, EMC running at 1866MHz, t186
1) without MT_NON_CACHEABLE: 30ms ~ 40ms
<3>[ 133.852885] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[ 133.860471] _tegra_set_vpr_params[120]: begin
<3>[ 133.896481] _tegra_set_vpr_params[123]: end
<3>[ 133.908944] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[ 133.916397] _tegra_set_vpr_params[120]: begin
<3>[ 133.956369] _tegra_set_vpr_params[123]: end
<3>[ 133.970394] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[ 133.977934] _tegra_set_vpr_params[120]: begin
<3>[ 134.013874] _tegra_set_vpr_params[123]: end
<3>[ 134.025666] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[ 134.033512] _tegra_set_vpr_params[120]: begin
<3>[ 134.065996] _tegra_set_vpr_params[123]: end
<3>[ 134.075465] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[ 134.082923] _tegra_set_vpr_params[120]: begin
<3>[ 134.113119] _tegra_set_vpr_params[123]: end
<3>[ 134.123448] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[ 134.130790] _tegra_set_vpr_params[120]: begin
<3>[ 134.162523] _tegra_set_vpr_params[123]: end
<3>[ 134.172413] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[ 134.179772] _tegra_set_vpr_params[120]: begin
<3>[ 134.209142] _tegra_set_vpr_params[123]: end

2) with MT_NON_CACHEABLE: 10ms ~ 18ms
<3>[ 102.108702] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[ 102.116296] _tegra_set_vpr_params[120]: begin
<3>[ 102.134272] _tegra_set_vpr_params[123]: end
<3>[ 102.145839] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[ 102.153226] _tegra_set_vpr_params[120]: begin
<3>[ 102.164201] _tegra_set_vpr_params[123]: end
<3>[ 102.172275] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[ 102.179638] _tegra_set_vpr_params[120]: begin
<3>[ 102.190342] _tegra_set_vpr_params[123]: end
<3>[ 102.197524] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[ 102.205085] _tegra_set_vpr_params[120]: begin
<3>[ 102.216112] _tegra_set_vpr_params[123]: end
<3>[ 102.224080] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[ 102.231387] _tegra_set_vpr_params[120]: begin
<3>[ 102.241775] _tegra_set_vpr_params[123]: end
<3>[ 102.248825] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[ 102.256069] _tegra_set_vpr_params[120]: begin
<3>[ 102.266368] _tegra_set_vpr_params[123]: end
<3>[ 102.273400] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[ 102.280672] _tegra_set_vpr_params[120]: begin
<3>[ 102.290929] _tegra_set_vpr_params[123]: end

Change-Id: I5f604064ce7b8b73ea9ad5860156ae5e2c6cc42a
Signed-off-by: Ken Chang <kenc@nvidia.com>

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Tegra: remove support for USE_COHERENT_MEM

This patch removes the support for 'USE_COHERENT_MEM' as
Tegra platforms no longer support the feature.

Change-Id: If1c80fc4e5974412572b3bc1fdf9e70b1ee5d4

Tegra: remove support for USE_COHERENT_MEM

This patch removes the support for 'USE_COHERENT_MEM' as
Tegra platforms no longer support the feature.

Change-Id: If1c80fc4e5974412572b3bc1fdf9e70b1ee5d4ec
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra: remove circular dependency with common_def.h

This patch stops including common_def.h from platform_def.h to
fix a circular depoendency between them.

This means platform_def.h now has to defi

Tegra: remove circular dependency with common_def.h

This patch stops including common_def.h from platform_def.h to
fix a circular depoendency between them.

This means platform_def.h now has to define the linker macros:
* PLATFORM_LINKER_FORMAT
* PLATFORM_LINKER_ARCH

Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: include missing stdbool.h

This patch includes the missing stdbool.h header from flowctrl.h
and bpmp_ivc.c files.

Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2
Signed-off-by: Varun Wad

Tegra: include missing stdbool.h

This patch includes the missing stdbool.h header from flowctrl.h
and bpmp_ivc.c files.

Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: remove support for SEPARATE_CODE_AND_RODATA=0

Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.

This patch uses the common macros provided by bl_common.h as a result
and add

Tegra: remove support for SEPARATE_CODE_AND_RODATA=0

Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.

This patch uses the common macros provided by bl_common.h as a result
and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set
to '1'.

Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Merge "fvp: use two instances of Cactus at S-EL1" into integration

Merge "spmc: manifest changes to support two sample cactus secure partitions" into integration

fvp: use two instances of Cactus at S-EL1

To demonstrate communication between SP's two instances of Cactus at
S-EL1 has been used.
This patch replaces Ivy SP with cactus-secondary SP which aligns w

fvp: use two instances of Cactus at S-EL1

To demonstrate communication between SP's two instances of Cactus at
S-EL1 has been used.
This patch replaces Ivy SP with cactus-secondary SP which aligns with
changes in tf-a-tests repository.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iee84f1f7f023b7c4f23fbc13682a42614a7f3707

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spmc: manifest changes to support two sample cactus secure partitions

When using the SPM Dispatcher, the SPMC sits as a BL32 component
(BL32_IMAGE_ID). The SPMC manifest is passed as the TOS fw conf

spmc: manifest changes to support two sample cactus secure partitions

When using the SPM Dispatcher, the SPMC sits as a BL32 component
(BL32_IMAGE_ID). The SPMC manifest is passed as the TOS fw config
component (TOS_FW_CONFIG_ID). It defines platform specific attributes
(memory range and physical CPU layout) as well as the attributes for
each secure partition (mostly load address). This manifest is passed
to the SPMC on boot up. An SP package contains the SP dtb in the SPCI
defined partition manifest format. As the SPMC manifest was enriched
it needs an increase of tos_fw-config max-size in fvp_fw_config dts.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia1dce00c6c4cbaa118fa56617980d32e2956a94e

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Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler

The 'plat_core_pos_by_mpidr' handler gets called very early during boot
and the compiler generated code overwrites the caller's regist

Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler

The 'plat_core_pos_by_mpidr' handler gets called very early during boot
and the compiler generated code overwrites the caller's registers.

This patch converts the 'plat_core_pos_by_mpidr' handler into an assembly
function and uses registers x0-x3, to fix this anomaly.

Change-Id: I8d974e007a0bad039defaf77b11a180d899ead3c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: reset power state info for CPUs

We set deepest power state when offlining a core but that may not be
requested by non-secure sw which controls idle states. It will re-init
this info from n

Tegra194: reset power state info for CPUs

We set deepest power state when offlining a core but that may not be
requested by non-secure sw which controls idle states. It will re-init
this info from non-secure software when the core come online.

This patch resets the power state in the non-secure world context
to allow it to start with a clean slate.

Change-Id: Iafd92cb2a49571aa6eeb9580beaaff4ba55a87dc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: system resume from TZSRAM memory

TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores t

Tegra186: system resume from TZSRAM memory

TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores the contents to TZSRAM during System Resume.

This patch removes the code that sets up CPU vector to point to
TZSRAM during System Resume as a result. The trampoline code can
also be completely removed as a result.

Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: disable PROGRAMMABLE_RESET_ADDRESS

This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the abi

Tegra186: disable PROGRAMMABLE_RESET_ADDRESS

This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.

Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: SE: switch SE clock source to CLK_M

In SE suspend, switch SE clock source to CLK_M,
to make sure SE clock is on when saving SE context

Change-Id: I57c559825a3ec8e0cc35f7a389afc458a5eed0cb

Tegra210: SE: switch SE clock source to CLK_M

In SE suspend, switch SE clock source to CLK_M,
to make sure SE clock is on when saving SE context

Change-Id: I57c559825a3ec8e0cc35f7a389afc458a5eed0cb
Signed-off-by: Leo He <leoh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: increase platform assert logging level to VERBOSE

This patch increases the assert logging level for all Tegra platforms
to VERBOSE, to print the actual assertion condition to the console,
imp

Tegra: increase platform assert logging level to VERBOSE

This patch increases the assert logging level for all Tegra platforms
to VERBOSE, to print the actual assertion condition to the console,
improving debuggability.

Change-Id: If3399bde63fa4261522cab984cc9c49cd2073358
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: enable dual execution for EL2 and EL3

This patch enables dual execution optimized translations for EL2 and EL3
CPU exception levels.

Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1
S

Tegra194: enable dual execution for EL2 and EL3

This patch enables dual execution optimized translations for EL2 and EL3
CPU exception levels.

Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: aarch64: calculate core position from one place

This patch updates 'plat_my_core_pos' handler to call
'plat_core_pos_from_mpidr' instead of implementing the same logic
at two places.

Change-

Tegra: aarch64: calculate core position from one place

This patch updates 'plat_my_core_pos' handler to call
'plat_core_pos_from_mpidr' instead of implementing the same logic
at two places.

Change-Id: I1e56adaa10dc2fe3440e5507e0e260d8932e6657
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra194: Update t194_nvg.h to v6.7

This patch updates the t194_nvg.h header file received from the CPU
team to v6.7.

Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774
Signed-off-by: Kalyani Chi

Tegra194: Update t194_nvg.h to v6.7

This patch updates the t194_nvg.h header file received from the CPU
team to v6.7.

Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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