1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 13 #include <tegra_def.h> 14 15 /******************************************************************************* 16 * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1 17 ******************************************************************************/ 18 #if !SEPARATE_CODE_AND_RODATA 19 #error "SEPARATE_CODE_AND_RODATA should be set to 1" 20 #endif 21 22 /* 23 * Platform binary types for linking 24 */ 25 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 26 #define PLATFORM_LINKER_ARCH aarch64 27 28 /******************************************************************************* 29 * Generic platform constants 30 ******************************************************************************/ 31 32 /* Size of cacheable stacks */ 33 #ifdef IMAGE_BL31 34 #define PLATFORM_STACK_SIZE U(0x400) 35 #endif 36 37 #define TEGRA_PRIMARY_CPU U(0x0) 38 39 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 40 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 41 PLATFORM_MAX_CPUS_PER_CLUSTER) 42 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 43 PLATFORM_CLUSTER_COUNT + 1) 44 45 /******************************************************************************* 46 * Platform console related constants 47 ******************************************************************************/ 48 #define TEGRA_CONSOLE_BAUDRATE U(115200) 49 #define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000) 50 #define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000) 51 52 /******************************************************************************* 53 * Platform memory map related constants 54 ******************************************************************************/ 55 /* Size of trusted dram */ 56 #define TZDRAM_SIZE U(0x00400000) 57 #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 58 59 /******************************************************************************* 60 * BL31 specific defines. 61 ******************************************************************************/ 62 #define BL31_SIZE U(0x40000) 63 #define BL31_BASE TZDRAM_BASE 64 #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 65 #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 66 #define BL32_LIMIT TZDRAM_END 67 68 /******************************************************************************* 69 * Some data must be aligned on the biggest cache line size in the platform. 70 * This is known only to the platform as it might have a combination of 71 * integrated and external caches. 72 ******************************************************************************/ 73 #define CACHE_WRITEBACK_SHIFT 6 74 #define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */ 75 76 /******************************************************************************* 77 * Dummy macros to compile io_storage support 78 ******************************************************************************/ 79 #define MAX_IO_DEVICES U(0) 80 #define MAX_IO_HANDLES U(0) 81 82 83 #endif /* PLATFORM_DEF_H */ 84