fconf: Extract Timer clock freq from HW_CONFIG dtb

Extract Timer clock frequency from the timer node in
HW_CONFIG dtb. The first timer is a per-core architected timer attached
to a GIC to deliver it

fconf: Extract Timer clock freq from HW_CONFIG dtb

Extract Timer clock frequency from the timer node in
HW_CONFIG dtb. The first timer is a per-core architected timer attached
to a GIC to deliver its per-processor interrupts via PPIs.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I2f4b27c48e4c79208dab9f03c768d9221ba6ca86

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plat/arm: Update the fw_config load call and populate it's information

Modified the code to do below changes:

1. Migrates the Arm platforms to the API changes introduced in the
previous patches

plat/arm: Update the fw_config load call and populate it's information

Modified the code to do below changes:

1. Migrates the Arm platforms to the API changes introduced in the
previous patches by fixing the fconf_load_config() call.
2. Retrieve dynamically the address of tb_fw_config using fconf
getter api which is subsequently used to write mbedTLS heap
address and BL2 hash data in the tb_fw_config DTB.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change-Id: I3c9d9345dcbfb99127c61d5589b4aa1532fbf4be

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fconf: Clean confused naming between TB_FW and FW_CONFIG

Cleaned up confused naming between TB_FW and FW_CONFIG.

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V B

fconf: Clean confused naming between TB_FW and FW_CONFIG

Cleaned up confused naming between TB_FW and FW_CONFIG.

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9e9f6e6ca076d38fee0388f97d370431ae067f08

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tbbr/dualroot: Add fw_config image in chain of trust

fw_config image is authenticated using secure boot framework by
adding it into the single root and dual root chain of trust.

The COT for fw_conf

tbbr/dualroot: Add fw_config image in chain of trust

fw_config image is authenticated using secure boot framework by
adding it into the single root and dual root chain of trust.

The COT for fw_config image looks as below:

+------------------+ +-------------------+
| ROTPK/ROTPK Hash |------>| Trusted Boot fw |
+------------------+ | Certificate |
| (Auth Image) |
/+-------------------+
/ |
/ |
/ |
/ |
L v
+------------------+ +-------------------+
| fw_config hash |------>| fw_config |
| | | (Data Image) |
+------------------+ +-------------------+

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I08fc8ee95c29a95bb140c807dd06e772474c7367

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plat/arm: Rentroduce tb_fw_config device tree

Moved BL2 configuration nodes from fw_config to newly
created tb_fw_config device tree.

fw_config device tree's main usage is to hold properties shared

plat/arm: Rentroduce tb_fw_config device tree

Moved BL2 configuration nodes from fw_config to newly
created tb_fw_config device tree.

fw_config device tree's main usage is to hold properties shared
across all BLx images.
An example is the "dtb-registry" node, which contains the
information about the other device tree configurations
(load-address, size).

Also, Updated load-address of tb_fw_config which is now located
after fw_config in SRAM.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ic398c86a4d822dacd55b5e25fd41d4fe3888d79a

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Fix usage of incorrect function name

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: Ic387630c096361ea9a963cde0018a0efb63e3bd2

stm32mp1: SP_MIN embeds Arm Architecture services

Embed Arch Architecture SMCCC services in stm32mp1 SP_MIN. This
service is needed by Linux kernel to setup the SMCCC conduit
used by its SCMI SMC tr

stm32mp1: SP_MIN embeds Arm Architecture services

Embed Arch Architecture SMCCC services in stm32mp1 SP_MIN. This
service is needed by Linux kernel to setup the SMCCC conduit
used by its SCMI SMC transport driver.

Change-Id: I454a7ef3048a77ab73fff945e8115b60445d5841
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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stm32mp1: use last page of SYSRAM as SCMI shared memory

SCMI shared memory is used to exchange message payloads between
secure SCMI services and non-secure SCMI agents. It is mapped
uncached (device

stm32mp1: use last page of SYSRAM as SCMI shared memory

SCMI shared memory is used to exchange message payloads between
secure SCMI services and non-secure SCMI agents. It is mapped
uncached (device) mainly to conform to existing support in
the Linux kernel. Note that executive messages are mostly short
(few 32bit words) hence not using cache will not penalize much
performances.

Platform stm32mp1 shall configure ETZPC to harden properly the
secure and non-secure areas of the SYSRAM address space, that before
CPU accesses the shared memory when mapped non-secure.

This change defines STM32MP_SEC_SYSRAM_BASE/STM32MP_SEC_SYSRAM_SIZE and
STM32MP_NS_SYSRAM_BASE/STM32MP_NS_SYSRAM_SIZE.

Change-Id: I71ff02a359b9668ae1c5a71b5f102cf3d310f289
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: check stronger the secondary CPU entry point

When using SP_min as monitor, only sp_min_warm_entrypoint() is a valid
secure entry point.

Change-Id: I440cec798e901b11a34dd482c33b2e378a8328a

stm32mp1: check stronger the secondary CPU entry point

When using SP_min as monitor, only sp_min_warm_entrypoint() is a valid
secure entry point.

Change-Id: I440cec798e901b11a34dd482c33b2e378a8328ab
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>

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stm32mp1: disable neon in sp_min

Disable use of Neon VFP support for platform stm32mp1 when
building with SP_MIN runtime services as these can conflict with
non-secure world use of NEON support. Thi

stm32mp1: disable neon in sp_min

Disable use of Neon VFP support for platform stm32mp1 when
building with SP_MIN runtime services as these can conflict with
non-secure world use of NEON support. This is preferred over a
systematic backup/restore of NEON context when switching
between non-secure and secure worlds.

When NEON support is disabled, this is done for both BL2 and BL32 as
build process uses common libraries built once for both binaries.

Change-Id: I4e8808dcb6ef58fc839e6f85fd6e45cfbaa34be0
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: shared resources: apply registered configuration

BL32/SP_MIN configures platform security hardening from the shared
resources driver. At the end of SP_MIN initialization, all shared
resou

stm32mp1: shared resources: apply registered configuration

BL32/SP_MIN configures platform security hardening from the shared
resources driver. At the end of SP_MIN initialization, all shared
resources shall be assigned to secure or non-secure world by
drivers. A lock prevent from further change on the resource
assignation. By definition, resources not registered are assign
to non-secure world since not claimed by any component on the BL.

No functional change as all resources are currently in state
SHRES_UNREGISTERED hence assigned to non-secure world as prior
this change in stm32mp1_etzpc_early_setup() and
sp_min_platform_setup().

Change-Id: Ic41fab47216c3b8b7a6a75b8358cfcec411ed941
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: shared resources: count GPIOZ bank pins

Get number of pins in the GPIOZ bank with helper function
fdt_get_gpio_bank_pin_count(). Save the value in RAM to prevent
parsing the FDT several ti

stm32mp1: shared resources: count GPIOZ bank pins

Get number of pins in the GPIOZ bank with helper function
fdt_get_gpio_bank_pin_count(). Save the value in RAM to prevent
parsing the FDT several time for the same information.

Change-Id: Ie68e300804461ffce09914100a7d2962116023b5
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: shared resources: define resource identifiers

Define enum stm32mp_shres for platform stm32mp1. The enumerated
type defines all resources that can be assigned to secure or
non-secure worlds

stm32mp1: shared resources: define resource identifiers

Define enum stm32mp_shres for platform stm32mp1. The enumerated
type defines all resources that can be assigned to secure or
non-secure worlds at run time for the platform.

Change-Id: I5de20d72735856645f1efd0993643278e8d35bcb
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: introduce shared resources support

STM32MP1 SoC includes peripheral interfaces that can be assigned to
the secure world, or that can be opened to the non-secure world.

This change introdu

stm32mp1: introduce shared resources support

STM32MP1 SoC includes peripheral interfaces that can be assigned to
the secure world, or that can be opened to the non-secure world.

This change introduces the basics of a driver that manages such
resources which assignation is done at run time. It currently offers
API functions that state whether a service exposed to non-secure
world has permission to access a targeted clock or reset controller.

Change-Id: Iff20028f41586bc501085488c03546ffe31046d8
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge changes from topic "tegra-memctrlv2-vpr-resize-bugfix" into integration

* changes:
Tegra: sanity check NS address and size before use
Tegra: memctrl_v2: fixup sequence to resize video memo

Merge changes from topic "tegra-memctrlv2-vpr-resize-bugfix" into integration

* changes:
Tegra: sanity check NS address and size before use
Tegra: memctrl_v2: fixup sequence to resize video memory

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Tegra: sanity check NS address and size before use

This patch updates the 'bl31_check_ns_address()' helper function to
check that the memory address and size passed by the NS world are not
zero.

Th

Tegra: sanity check NS address and size before use

This patch updates the 'bl31_check_ns_address()' helper function to
check that the memory address and size passed by the NS world are not
zero.

The helper fucntion also returns the error code as soon as it detects
inconsistencies, to avoid multiple error paths from kicking in for the
same input parameters.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Change-Id: I46264f913954614bedcbde12e47ea0c70cd19be0

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plat: marvell: armada: a8k: add OP-TEE OS MMU tables

Adjust the latest OP-TEE memory definitions to the
newest TF-A baseline.

Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36
Signed-off-by: Kon

plat: marvell: armada: a8k: add OP-TEE OS MMU tables

Adjust the latest OP-TEE memory definitions to the
newest TF-A baseline.

Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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drivers: marvell: add support for mapping the entire LLC to SRAM

Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - d

drivers: marvell: add support for mapping the entire LLC to SRAM

Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - disabled
by the default.
Add description of LLC_SRAM flag to the build documentation.

Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms

Extend the CCU tables with secure SRAM window in all board
setups that uses SoCs based on AP806/AP807 North Bridges

Change-Id

plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms

Extend the CCU tables with secure SRAM window in all board
setups that uses SoCs based on AP806/AP807 North Bridges

Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: reduce memory size reserved for FIP image

It is not needed to reserve 64MB for FIP. Limit this to 4MB
for both supported Armada SoC families.

Change-Id: I58a8ce4408a646fe1afd

plat: marvell: armada: reduce memory size reserved for FIP image

It is not needed to reserve 64MB for FIP. Limit this to 4MB
for both supported Armada SoC families.

Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[Extract from bigger commit]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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plat: marvell: armada: platform definitions cleanup

- Remove
TRUSTED_DRAM_BASE
TRUSTED_DRAM_SIZE
MARVELL_TRUSTED_SRAM_BASE
- Rename
PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTE

plat: marvell: armada: platform definitions cleanup

- Remove
TRUSTED_DRAM_BASE
TRUSTED_DRAM_SIZE
MARVELL_TRUSTED_SRAM_BASE
- Rename
PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_*
PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_*
MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM
- Move
MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h
- Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map
- Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM
- Add minor style improvents

Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[Improve patch after rebase]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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plat: marvell: armada: a8k: check CCU window state before loading MSS BL2

Make sure the current CCU window is not in use before adding
a new address map during MSS BL2 image load preparations.
At BL

plat: marvell: armada: a8k: check CCU window state before loading MSS BL2

Make sure the current CCU window is not in use before adding
a new address map during MSS BL2 image load preparations.
At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is
added to MSS BL2 stage initialization, the DDR entry will be destroyed
and lead to the system hang.

Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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drivers: marvell: align and extend llc macros

Make all LLC-related macros to start with the same prefix
Add more LLC control registers definitions
This patch is a preparation step for LLC SRAM suppo

drivers: marvell: align and extend llc macros

Make all LLC-related macros to start with the same prefix
Add more LLC control registers definitions
This patch is a preparation step for LLC SRAM support

Change-Id: I0a4f0fc83e8ef35be93dd239a85f2a9f88d1ab19
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: a8k: move address config of cp1/2 to BL2

The configuration space of each standalone CP was updated in BL31.
Loading FW procedure take places earlier in SCP_BL2.
It needs to be done af

plat: marvell: a8k: move address config of cp1/2 to BL2

The configuration space of each standalone CP was updated in BL31.
Loading FW procedure take places earlier in SCP_BL2.
It needs to be done after access to each CP is provided.
Moving the proper configuration from BL31 to BL2 solves it.

Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea
Signed-off-by: Ben Peled <bpeled@marvell.com>

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plat: marvell: armada: re-enable BL32_BASE definition

As a preparation to support proper loading the OPTEE OS image,
enable the BL32 specific defines in case the SPD is used.

On the occasion move t

plat: marvell: armada: re-enable BL32_BASE definition

As a preparation to support proper loading the OPTEE OS image,
enable the BL32 specific defines in case the SPD is used.

On the occasion move two BL32-related macros to marvell_def.h
and fix BL32_LIMIT definition.

Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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