1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #include <stm32mp1_shared_resources.h> 29 #endif 30 31 /******************************************************************************* 32 * CHIP ID 33 ******************************************************************************/ 34 #define STM32MP157C_PART_NB U(0x05000000) 35 #define STM32MP157A_PART_NB U(0x05000001) 36 #define STM32MP153C_PART_NB U(0x05000024) 37 #define STM32MP153A_PART_NB U(0x05000025) 38 #define STM32MP151C_PART_NB U(0x0500002E) 39 #define STM32MP151A_PART_NB U(0x0500002F) 40 41 #define STM32MP1_REV_B U(0x2000) 42 43 /******************************************************************************* 44 * PACKAGE ID 45 ******************************************************************************/ 46 #define PKG_AA_LFBGA448 U(4) 47 #define PKG_AB_LFBGA354 U(3) 48 #define PKG_AC_TFBGA361 U(2) 49 #define PKG_AD_TFBGA257 U(1) 50 51 /******************************************************************************* 52 * STM32MP1 memory map related constants 53 ******************************************************************************/ 54 #define STM32MP_ROM_BASE U(0x00000000) 55 #define STM32MP_ROM_SIZE U(0x00020000) 56 57 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 58 #define STM32MP_SYSRAM_SIZE U(0x00040000) 59 60 /* DDR configuration */ 61 #define STM32MP_DDR_BASE U(0xC0000000) 62 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 63 #ifdef AARCH32_SP_OPTEE 64 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 65 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 66 #else 67 #define STM32MP_DDR_S_SIZE U(0) 68 #define STM32MP_DDR_SHMEM_SIZE U(0) 69 #endif 70 71 /* DDR power initializations */ 72 #ifndef __ASSEMBLER__ 73 enum ddr_type { 74 STM32MP_DDR3, 75 STM32MP_LPDDR2, 76 STM32MP_LPDDR3 77 }; 78 #endif 79 80 /* Section used inside TF binaries */ 81 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 82 /* 256 Octets reserved for header */ 83 #define STM32MP_HEADER_SIZE U(0x00000100) 84 85 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 86 STM32MP_PARAM_LOAD_SIZE + \ 87 STM32MP_HEADER_SIZE) 88 89 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 90 (STM32MP_PARAM_LOAD_SIZE + \ 91 STM32MP_HEADER_SIZE)) 92 93 #ifdef AARCH32_SP_OPTEE 94 #define STM32MP_BL32_SIZE U(0) 95 96 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 97 98 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 99 STM32MP_OPTEE_BASE) 100 #else 101 #if STACK_PROTECTOR_ENABLED 102 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */ 103 #else 104 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */ 105 #endif 106 #endif 107 108 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 109 STM32MP_SYSRAM_SIZE - \ 110 STM32MP_BL32_SIZE) 111 112 #ifdef AARCH32_SP_OPTEE 113 #if STACK_PROTECTOR_ENABLED 114 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */ 115 #else 116 #define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */ 117 #endif 118 #else 119 #if STACK_PROTECTOR_ENABLED 120 #define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */ 121 #else 122 #define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */ 123 #endif 124 #endif 125 126 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 127 STM32MP_BL2_SIZE) 128 129 /* BL2 and BL32/sp_min require 4 tables */ 130 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 131 132 /* 133 * MAX_MMAP_REGIONS is usually: 134 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 135 */ 136 #if defined(IMAGE_BL2) 137 #define MAX_MMAP_REGIONS 11 138 #endif 139 #if defined(IMAGE_BL32) 140 #define MAX_MMAP_REGIONS 6 141 #endif 142 143 /* DTB initialization value */ 144 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 145 146 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 147 STM32MP_DTB_SIZE) 148 149 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 150 151 /* Define maximum page size for NAND devices */ 152 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 153 154 /******************************************************************************* 155 * STM32MP1 RAW partition offset for MTD devices 156 ******************************************************************************/ 157 #define STM32MP_NOR_BL33_OFFSET U(0x00080000) 158 #ifdef AARCH32_SP_OPTEE 159 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000) 160 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000) 161 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000) 162 #endif 163 164 #define STM32MP_NAND_BL33_OFFSET U(0x00200000) 165 #ifdef AARCH32_SP_OPTEE 166 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000) 167 #define STM32MP_NAND_TEED_OFFSET U(0x00680000) 168 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000) 169 #endif 170 171 /******************************************************************************* 172 * STM32MP1 device/io map related constants (used for MMU) 173 ******************************************************************************/ 174 #define STM32MP1_DEVICE1_BASE U(0x40000000) 175 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 176 177 #define STM32MP1_DEVICE2_BASE U(0x80000000) 178 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 179 180 /******************************************************************************* 181 * STM32MP1 RCC 182 ******************************************************************************/ 183 #define RCC_BASE U(0x50000000) 184 185 /******************************************************************************* 186 * STM32MP1 PWR 187 ******************************************************************************/ 188 #define PWR_BASE U(0x50001000) 189 190 /******************************************************************************* 191 * STM32MP1 GPIO 192 ******************************************************************************/ 193 #define GPIOA_BASE U(0x50002000) 194 #define GPIOB_BASE U(0x50003000) 195 #define GPIOC_BASE U(0x50004000) 196 #define GPIOD_BASE U(0x50005000) 197 #define GPIOE_BASE U(0x50006000) 198 #define GPIOF_BASE U(0x50007000) 199 #define GPIOG_BASE U(0x50008000) 200 #define GPIOH_BASE U(0x50009000) 201 #define GPIOI_BASE U(0x5000A000) 202 #define GPIOJ_BASE U(0x5000B000) 203 #define GPIOK_BASE U(0x5000C000) 204 #define GPIOZ_BASE U(0x54004000) 205 #define GPIO_BANK_OFFSET U(0x1000) 206 207 /* Bank IDs used in GPIO driver API */ 208 #define GPIO_BANK_A U(0) 209 #define GPIO_BANK_B U(1) 210 #define GPIO_BANK_C U(2) 211 #define GPIO_BANK_D U(3) 212 #define GPIO_BANK_E U(4) 213 #define GPIO_BANK_F U(5) 214 #define GPIO_BANK_G U(6) 215 #define GPIO_BANK_H U(7) 216 #define GPIO_BANK_I U(8) 217 #define GPIO_BANK_J U(9) 218 #define GPIO_BANK_K U(10) 219 #define GPIO_BANK_Z U(25) 220 221 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 222 223 /******************************************************************************* 224 * STM32MP1 UART 225 ******************************************************************************/ 226 #define USART1_BASE U(0x5C000000) 227 #define USART2_BASE U(0x4000E000) 228 #define USART3_BASE U(0x4000F000) 229 #define UART4_BASE U(0x40010000) 230 #define UART5_BASE U(0x40011000) 231 #define USART6_BASE U(0x44003000) 232 #define UART7_BASE U(0x40018000) 233 #define UART8_BASE U(0x40019000) 234 #define STM32MP_UART_BAUDRATE U(115200) 235 236 /* For UART crash console */ 237 #define STM32MP_DEBUG_USART_BASE UART4_BASE 238 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 239 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 240 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 241 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 242 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 243 #define DEBUG_UART_TX_GPIO_PORT 11 244 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 245 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 246 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 247 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 248 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 249 250 /******************************************************************************* 251 * STM32MP1 ETZPC 252 ******************************************************************************/ 253 #define STM32MP1_ETZPC_BASE U(0x5C007000) 254 255 /* ETZPC TZMA IDs */ 256 #define STM32MP1_ETZPC_TZMA_ROM U(0) 257 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 258 259 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 260 261 /* ETZPC DECPROT IDs */ 262 #define STM32MP1_ETZPC_STGENC_ID 0 263 #define STM32MP1_ETZPC_BKPSRAM_ID 1 264 #define STM32MP1_ETZPC_IWDG1_ID 2 265 #define STM32MP1_ETZPC_USART1_ID 3 266 #define STM32MP1_ETZPC_SPI6_ID 4 267 #define STM32MP1_ETZPC_I2C4_ID 5 268 #define STM32MP1_ETZPC_RNG1_ID 7 269 #define STM32MP1_ETZPC_HASH1_ID 8 270 #define STM32MP1_ETZPC_CRYP1_ID 9 271 #define STM32MP1_ETZPC_DDRCTRL_ID 10 272 #define STM32MP1_ETZPC_DDRPHYC_ID 11 273 #define STM32MP1_ETZPC_I2C6_ID 12 274 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 275 276 #define STM32MP1_ETZPC_TIM2_ID 16 277 #define STM32MP1_ETZPC_TIM3_ID 17 278 #define STM32MP1_ETZPC_TIM4_ID 18 279 #define STM32MP1_ETZPC_TIM5_ID 19 280 #define STM32MP1_ETZPC_TIM6_ID 20 281 #define STM32MP1_ETZPC_TIM7_ID 21 282 #define STM32MP1_ETZPC_TIM12_ID 22 283 #define STM32MP1_ETZPC_TIM13_ID 23 284 #define STM32MP1_ETZPC_TIM14_ID 24 285 #define STM32MP1_ETZPC_LPTIM1_ID 25 286 #define STM32MP1_ETZPC_WWDG1_ID 26 287 #define STM32MP1_ETZPC_SPI2_ID 27 288 #define STM32MP1_ETZPC_SPI3_ID 28 289 #define STM32MP1_ETZPC_SPDIFRX_ID 29 290 #define STM32MP1_ETZPC_USART2_ID 30 291 #define STM32MP1_ETZPC_USART3_ID 31 292 #define STM32MP1_ETZPC_UART4_ID 32 293 #define STM32MP1_ETZPC_UART5_ID 33 294 #define STM32MP1_ETZPC_I2C1_ID 34 295 #define STM32MP1_ETZPC_I2C2_ID 35 296 #define STM32MP1_ETZPC_I2C3_ID 36 297 #define STM32MP1_ETZPC_I2C5_ID 37 298 #define STM32MP1_ETZPC_CEC_ID 38 299 #define STM32MP1_ETZPC_DAC_ID 39 300 #define STM32MP1_ETZPC_UART7_ID 40 301 #define STM32MP1_ETZPC_UART8_ID 41 302 #define STM32MP1_ETZPC_MDIOS_ID 44 303 #define STM32MP1_ETZPC_TIM1_ID 48 304 #define STM32MP1_ETZPC_TIM8_ID 49 305 #define STM32MP1_ETZPC_USART6_ID 51 306 #define STM32MP1_ETZPC_SPI1_ID 52 307 #define STM32MP1_ETZPC_SPI4_ID 53 308 #define STM32MP1_ETZPC_TIM15_ID 54 309 #define STM32MP1_ETZPC_TIM16_ID 55 310 #define STM32MP1_ETZPC_TIM17_ID 56 311 #define STM32MP1_ETZPC_SPI5_ID 57 312 #define STM32MP1_ETZPC_SAI1_ID 58 313 #define STM32MP1_ETZPC_SAI2_ID 59 314 #define STM32MP1_ETZPC_SAI3_ID 60 315 #define STM32MP1_ETZPC_DFSDM_ID 61 316 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 317 #define STM32MP1_ETZPC_LPTIM2_ID 64 318 #define STM32MP1_ETZPC_LPTIM3_ID 65 319 #define STM32MP1_ETZPC_LPTIM4_ID 66 320 #define STM32MP1_ETZPC_LPTIM5_ID 67 321 #define STM32MP1_ETZPC_SAI4_ID 68 322 #define STM32MP1_ETZPC_VREFBUF_ID 69 323 #define STM32MP1_ETZPC_DCMI_ID 70 324 #define STM32MP1_ETZPC_CRC2_ID 71 325 #define STM32MP1_ETZPC_ADC_ID 72 326 #define STM32MP1_ETZPC_HASH2_ID 73 327 #define STM32MP1_ETZPC_RNG2_ID 74 328 #define STM32MP1_ETZPC_CRYP2_ID 75 329 #define STM32MP1_ETZPC_SRAM1_ID 80 330 #define STM32MP1_ETZPC_SRAM2_ID 81 331 #define STM32MP1_ETZPC_SRAM3_ID 82 332 #define STM32MP1_ETZPC_SRAM4_ID 83 333 #define STM32MP1_ETZPC_RETRAM_ID 84 334 #define STM32MP1_ETZPC_OTG_ID 85 335 #define STM32MP1_ETZPC_SDMMC3_ID 86 336 #define STM32MP1_ETZPC_DLYBSD3_ID 87 337 #define STM32MP1_ETZPC_DMA1_ID 88 338 #define STM32MP1_ETZPC_DMA2_ID 89 339 #define STM32MP1_ETZPC_DMAMUX_ID 90 340 #define STM32MP1_ETZPC_FMC_ID 91 341 #define STM32MP1_ETZPC_QSPI_ID 92 342 #define STM32MP1_ETZPC_DLYBQ_ID 93 343 #define STM32MP1_ETZPC_ETH_ID 94 344 #define STM32MP1_ETZPC_RSV_ID 95 345 346 #define STM32MP_ETZPC_MAX_ID 96 347 348 /******************************************************************************* 349 * STM32MP1 TZC (TZ400) 350 ******************************************************************************/ 351 #define STM32MP1_TZC_BASE U(0x5C006000) 352 353 #define STM32MP1_TZC_A7_ID U(0) 354 #define STM32MP1_TZC_M4_ID U(1) 355 #define STM32MP1_TZC_LCD_ID U(3) 356 #define STM32MP1_TZC_GPU_ID U(4) 357 #define STM32MP1_TZC_MDMA_ID U(5) 358 #define STM32MP1_TZC_DMA_ID U(6) 359 #define STM32MP1_TZC_USB_HOST_ID U(7) 360 #define STM32MP1_TZC_USB_OTG_ID U(8) 361 #define STM32MP1_TZC_SDMMC_ID U(9) 362 #define STM32MP1_TZC_ETH_ID U(10) 363 #define STM32MP1_TZC_DAP_ID U(15) 364 365 #define STM32MP1_FILTER_BIT_ALL U(3) 366 367 /******************************************************************************* 368 * STM32MP1 SDMMC 369 ******************************************************************************/ 370 #define STM32MP_SDMMC1_BASE U(0x58005000) 371 #define STM32MP_SDMMC2_BASE U(0x58007000) 372 #define STM32MP_SDMMC3_BASE U(0x48004000) 373 374 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 375 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 376 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 377 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 378 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 379 380 /******************************************************************************* 381 * STM32MP1 BSEC / OTP 382 ******************************************************************************/ 383 #define STM32MP1_OTP_MAX_ID 0x5FU 384 #define STM32MP1_UPPER_OTP_START 0x20U 385 386 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 387 388 /* OTP offsets */ 389 #define DATA0_OTP U(0) 390 #define PART_NUMBER_OTP U(1) 391 #define NAND_OTP U(9) 392 #define PACKAGE_OTP U(16) 393 #define HW2_OTP U(18) 394 395 /* OTP mask */ 396 /* DATA0 */ 397 #define DATA0_OTP_SECURED BIT(6) 398 399 /* PART NUMBER */ 400 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 401 #define PART_NUMBER_OTP_PART_SHIFT 0 402 403 /* PACKAGE */ 404 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 405 #define PACKAGE_OTP_PKG_SHIFT 27 406 407 /* IWDG OTP */ 408 #define HW2_OTP_IWDG_HW_POS U(3) 409 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 410 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 411 412 /* HW2 OTP */ 413 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 414 415 /* NAND OTP */ 416 /* NAND parameter storage flag */ 417 #define NAND_PARAM_STORED_IN_OTP BIT(31) 418 419 /* NAND page size in bytes */ 420 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 421 #define NAND_PAGE_SIZE_SHIFT 29 422 #define NAND_PAGE_SIZE_2K U(0) 423 #define NAND_PAGE_SIZE_4K U(1) 424 #define NAND_PAGE_SIZE_8K U(2) 425 426 /* NAND block size in pages */ 427 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 428 #define NAND_BLOCK_SIZE_SHIFT 27 429 #define NAND_BLOCK_SIZE_64_PAGES U(0) 430 #define NAND_BLOCK_SIZE_128_PAGES U(1) 431 #define NAND_BLOCK_SIZE_256_PAGES U(2) 432 433 /* NAND number of block (in unit of 256 blocs) */ 434 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 435 #define NAND_BLOCK_NB_SHIFT 19 436 #define NAND_BLOCK_NB_UNIT U(256) 437 438 /* NAND bus width in bits */ 439 #define NAND_WIDTH_MASK BIT(18) 440 #define NAND_WIDTH_SHIFT 18 441 442 /* NAND number of ECC bits per 512 bytes */ 443 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 444 #define NAND_ECC_BIT_NB_SHIFT 15 445 #define NAND_ECC_BIT_NB_UNSET U(0) 446 #define NAND_ECC_BIT_NB_1_BITS U(1) 447 #define NAND_ECC_BIT_NB_4_BITS U(2) 448 #define NAND_ECC_BIT_NB_8_BITS U(3) 449 #define NAND_ECC_ON_DIE U(4) 450 451 /* NAND number of planes */ 452 #define NAND_PLANE_BIT_NB_MASK BIT(14) 453 454 /******************************************************************************* 455 * STM32MP1 TAMP 456 ******************************************************************************/ 457 #define TAMP_BASE U(0x5C00A000) 458 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 459 460 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 461 static inline uint32_t tamp_bkpr(uint32_t idx) 462 { 463 return TAMP_BKP_REGISTER_BASE + (idx << 2); 464 } 465 #endif 466 467 /******************************************************************************* 468 * STM32MP1 DDRCTRL 469 ******************************************************************************/ 470 #define DDRCTRL_BASE U(0x5A003000) 471 472 /******************************************************************************* 473 * STM32MP1 DDRPHYC 474 ******************************************************************************/ 475 #define DDRPHYC_BASE U(0x5A004000) 476 477 /******************************************************************************* 478 * STM32MP1 IWDG 479 ******************************************************************************/ 480 #define IWDG_MAX_INSTANCE U(2) 481 #define IWDG1_INST U(0) 482 #define IWDG2_INST U(1) 483 484 #define IWDG1_BASE U(0x5C003000) 485 #define IWDG2_BASE U(0x5A002000) 486 487 /******************************************************************************* 488 * STM32MP1 I2C4 489 ******************************************************************************/ 490 #define I2C4_BASE U(0x5C002000) 491 492 /******************************************************************************* 493 * STM32MP1 DBGMCU 494 ******************************************************************************/ 495 #define DBGMCU_BASE U(0x50081000) 496 497 /******************************************************************************* 498 * Device Tree defines 499 ******************************************************************************/ 500 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 501 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 502 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 503 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 504 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 505 506 #endif /* STM32MP1_DEF_H */ 507