1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/gicv2.h> 17 #include <drivers/arm/tzc400.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/st/bsec.h> 20 #include <drivers/st/etzpc.h> 21 #include <drivers/st/stm32_console.h> 22 #include <drivers/st/stm32_gpio.h> 23 #include <drivers/st/stm32_iwdg.h> 24 #include <drivers/st/stm32mp1_clk.h> 25 #include <dt-bindings/clock/stm32mp1-clks.h> 26 #include <lib/el3_runtime/context_mgmt.h> 27 #include <lib/mmio.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 #include <plat/common/platform.h> 30 31 #include <platform_sp_min.h> 32 33 /****************************************************************************** 34 * Placeholder variables for copying the arguments that have been passed to 35 * BL32 from BL2. 36 ******************************************************************************/ 37 static entry_point_info_t bl33_image_ep_info; 38 39 static console_t console; 40 41 /******************************************************************************* 42 * Interrupt handler for FIQ (secure IRQ) 43 ******************************************************************************/ 44 void sp_min_plat_fiq_handler(uint32_t id) 45 { 46 switch (id & INT_ID_MASK) { 47 case STM32MP1_IRQ_TZC400: 48 ERROR("STM32MP1_IRQ_TZC400 generated\n"); 49 panic(); 50 break; 51 case STM32MP1_IRQ_AXIERRIRQ: 52 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n"); 53 panic(); 54 break; 55 default: 56 ERROR("SECURE IT handler not define for it : %u", id); 57 break; 58 } 59 } 60 61 /******************************************************************************* 62 * Return a pointer to the 'entry_point_info' structure of the next image for 63 * the security state specified. BL33 corresponds to the non-secure image type 64 * while BL32 corresponds to the secure image type. A NULL pointer is returned 65 * if the image does not exist. 66 ******************************************************************************/ 67 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 68 { 69 entry_point_info_t *next_image_info; 70 71 next_image_info = &bl33_image_ep_info; 72 73 if (next_image_info->pc == 0U) { 74 return NULL; 75 } 76 77 return next_image_info; 78 } 79 80 #define TZMA1_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE 81 #define TZMA0_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE 82 83 static void stm32mp1_etzpc_early_setup(void) 84 { 85 if (etzpc_init() != 0) { 86 panic(); 87 } 88 89 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_ROM, TZMA0_SECURE_RANGE); 90 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_SYSRAM, TZMA1_SECURE_RANGE); 91 } 92 93 /******************************************************************************* 94 * Perform any BL32 specific platform actions. 95 ******************************************************************************/ 96 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 97 u_register_t arg2, u_register_t arg3) 98 { 99 struct dt_node_info dt_uart_info; 100 int result; 101 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 102 103 /* Imprecise aborts can be masked in NonSecure */ 104 write_scr(read_scr() | SCR_AW_BIT); 105 106 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 107 BL_CODE_END - BL_CODE_BASE, 108 MT_CODE | MT_SECURE); 109 110 configure_mmu(); 111 112 assert(params_from_bl2 != NULL); 113 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 114 assert(params_from_bl2->h.version >= VERSION_2); 115 116 bl_params_node_t *bl_params = params_from_bl2->head; 117 118 /* 119 * Copy BL33 entry point information. 120 * They are stored in Secure RAM, in BL2's address space. 121 */ 122 while (bl_params != NULL) { 123 if (bl_params->image_id == BL33_IMAGE_ID) { 124 bl33_image_ep_info = *bl_params->ep_info; 125 break; 126 } 127 128 bl_params = bl_params->next_params_info; 129 } 130 131 if (dt_open_and_check() < 0) { 132 panic(); 133 } 134 135 if (bsec_probe() != 0) { 136 panic(); 137 } 138 139 if (stm32mp1_clk_probe() < 0) { 140 panic(); 141 } 142 143 result = dt_get_stdout_uart_info(&dt_uart_info); 144 145 if ((result > 0) && (dt_uart_info.status != 0U)) { 146 unsigned int console_flags; 147 148 if (console_stm32_register(dt_uart_info.base, 0, 149 STM32MP_UART_BAUDRATE, &console) == 150 0) { 151 panic(); 152 } 153 154 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | 155 CONSOLE_FLAG_TRANSLATE_CRLF; 156 #ifdef DEBUG 157 console_flags |= CONSOLE_FLAG_RUNTIME; 158 #endif 159 console_set_scope(&console, console_flags); 160 } 161 162 stm32mp1_etzpc_early_setup(); 163 } 164 165 /******************************************************************************* 166 * Initialize the MMU, security and the GIC. 167 ******************************************************************************/ 168 void sp_min_platform_setup(void) 169 { 170 /* Initialize tzc400 after DDR initialization */ 171 stm32mp1_security_setup(); 172 173 generic_delay_timer_init(); 174 175 stm32mp1_gic_init(); 176 177 if (stm32_iwdg_init() < 0) { 178 panic(); 179 } 180 181 stm32mp_lock_periph_registering(); 182 } 183 184 void sp_min_plat_arch_setup(void) 185 { 186 } 187