plat: marvell: armada: a8k: change CCU LLC SRAM mapping

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
unt

plat: marvell: armada: a8k: change CCU LLC SRAM mapping

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)

Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS

Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.

Change-Id: If8edeeec5861b52

plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS

Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.

Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: move mg conf related code to appropriate driver

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Si

plat: marvell: armada: move mg conf related code to appropriate driver

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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drivers: marvell: mg_conf_cm3: add basic driver

Implement function which will allow to start AP FW.

Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semiha

drivers: marvell: mg_conf_cm3: add basic driver

Implement function which will allow to start AP FW.

Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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plat: imx8mp: Add the basic support for i.MX8MP

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Ma

plat: imx8mp: Add the basic support for i.MX8MP

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core Arm Cortex-A53 cluster and
Cortex-M7 low-power coprocessor, audio digital signal processor, machine
learning and graphics accelerators.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a

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plat/arm, dts: Update platform device tree for CoT

Included cot_descriptors.dtsi in platform device tree
(fvp_tb_fw_config.dts).

Also, updated the maximum size of tb_fw_config to 0x1800
in order to

plat/arm, dts: Update platform device tree for CoT

Included cot_descriptors.dtsi in platform device tree
(fvp_tb_fw_config.dts).

Also, updated the maximum size of tb_fw_config to 0x1800
in order to accomodate the device tree for CoT descriptors.

Follow up patch will parse the device tree for these CoT descriptors
and fill the CoT descriptor structures at runtime instead of using
static CoT descriptor structures in the code base.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I90122bc713f6842b82fb019b04caf42629b4f45a

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plat: imx8m: Move the gpc hw reg to a separate header file

Although the GPC provides the similar functions for all the
i.MX8M SoC family, the HW register offset and bit defines
still have some sligh

plat: imx8m: Move the gpc hw reg to a separate header file

Although the GPC provides the similar functions for all the
i.MX8M SoC family, the HW register offset and bit defines
still have some slight difference, so move the hw reg
offset & most of the bitfield defines in 'gpc_reg.h' that
is specific to each SoC.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I291c435fe98c2f6e6ff8fe0c715ff3a83daa6a0f

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arm_fpga: Predefine DTB and BL33 load addresses

The memory layout for the FPGA is fairly uniform for most of the FPGA
images, and we already assume that DRAM starts at 2GB by default.

Prepopulate P

arm_fpga: Predefine DTB and BL33 load addresses

The memory layout for the FPGA is fairly uniform for most of the FPGA
images, and we already assume that DRAM starts at 2GB by default.

Prepopulate PRELOADED_BL33_BASE and FPGA_PRELOADED_DTB_BASE to some
sane default values, to simplify building some stock image.
If people want to deviate from that, they can always override those
addresses on the make command line.

Change-Id: I2238fafb3f8253a01ad2d88d45827c141d9b29dd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Add Klein and Matterhorn support

To support FPGAs with those cores as well, as the respective cpulib
files to the Makefile.

Change-Id: I1a60867d5937be88b32b210c7817be4274554a76
Signed-off

arm_fpga: Add Klein and Matterhorn support

To support FPGAs with those cores as well, as the respective cpulib
files to the Makefile.

Change-Id: I1a60867d5937be88b32b210c7817be4274554a76
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Support more CPU clusters

The maximum number of clusters is currently set to 2, which is quite
limiting. As there are FPGA images with 4 clusters, let's increase the
limit to 4.

Change-Id

arm_fpga: Support more CPU clusters

The maximum number of clusters is currently set to 2, which is quite
limiting. As there are FPGA images with 4 clusters, let's increase the
limit to 4.

Change-Id: I9a85ca07ebbd2a018ad9668536d867ad6b75e537
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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stm32mp1: register shared resource per GPIO bank/pin

Introduce helper functions stm32mp_register_secure_gpio() and
stm32mp_register_non_secure_gpio() for drivers to register a
GPIO pin as secure or

stm32mp1: register shared resource per GPIO bank/pin

Introduce helper functions stm32mp_register_secure_gpio() and
stm32mp_register_non_secure_gpio() for drivers to register a
GPIO pin as secure or non-secure.

These functions are stubbed when shared resource driver is not
embedded in the BL image so that drivers do not bother whether they
shall register or not their resources.

Change-Id: I1fe98576c072ae31f75427c9ac5c9f6c4f1b6ed1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: register shared resource per IOMEM address

Introduce helper functions stm32mp_register_secure_periph_iomem()
and stm32mp_register_non_secure_periph_iomem() for drivers to
register a resour

stm32mp1: register shared resource per IOMEM address

Introduce helper functions stm32mp_register_secure_periph_iomem()
and stm32mp_register_non_secure_periph_iomem() for drivers to
register a resource as secure or non-secure based on its SoC
interface registers base address.

These functions are stubbed when shared resources driver is not
embedded (!STM32MP_SHARED_RESOURCES) so that drivers embedded
in other BL stages do not bother whether they shall register or
not their resources.

Change-Id: Icebd05a930afc5964bc4677357da5d1b23666066
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: allow non-secure access to reset upon periph registration

Update implementation of stm32mp_nsec_can_access_reset() based
on the registering of the shared resources.

Querying registering s

stm32mp1: allow non-secure access to reset upon periph registration

Update implementation of stm32mp_nsec_can_access_reset() based
on the registering of the shared resources.

Querying registering state locks further registration of
peripherals.

Change-Id: I5f38f2a3481780b9a71939d95984c4821c537aa4
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: allow non-secure access to clocks upon periph registration

Update implementation of stm32mp_nsec_can_access_clock() based
on the registering of the shared resources.

Querying registering

stm32mp1: allow non-secure access to clocks upon periph registration

Update implementation of stm32mp_nsec_can_access_clock() based
on the registering of the shared resources.

Querying registering state locks further registration of peripherals.

Change-Id: If68f6d4a52c4742ba66244c6ea2d9afa08404137
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: shared resources: peripheral registering

Define helper functions stm32mp_register_secure_periph() and
stm32mp_register_non_secure_periph() for platform drivers to
register a shared resourc

stm32mp1: shared resources: peripheral registering

Define helper functions stm32mp_register_secure_periph() and
stm32mp_register_non_secure_periph() for platform drivers to
register a shared resource assigned to respectively secure
or non-secure world.

Some resources are related to clock resources. When a resource is
registered as secure, ensure its clock dependencies are also
registered as secure. Registering a non-secure resource does not
mandate its clock dependencies are also registered as non-secure.

Change-Id: I74975be8976b8d3bf18dcc807541a072803af6e3
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: shared resources: add trace messages

Define from helper functions to get a human readable string
identifier from a shared resource enumerated ID. Use them to
make debug traces more friendl

stm32mp1: shared resources: add trace messages

Define from helper functions to get a human readable string
identifier from a shared resource enumerated ID. Use them to
make debug traces more friendly peripheral registering functions.

Change-Id: I9e207b8ce1d1e9250e242ca7e15461b9a1532f40
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge "Upgrade libfdt source files" into integration

Merge "corstone700: splitting the platform support into FVP and FPGA" into integration

corstone700: splitting the platform support into FVP and FPGA

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

fvp and fpga

- Since the FVP and F

corstone700: splitting the platform support into FVP and FPGA

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

fvp and fpga

- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
- Enabling NEED_BL33 option
- Fixing non-secure image base: For no preloaded bl33 we want to
have the NS base set on shared ram. Setup a memory map region
for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY

Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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rockchip: don't crash if we get an FDT we can't parse

When we parse the param from BL2, we try to parse it as a FDT and then,
if that fails, as aux params. However, we don't sufficiently distinguish

rockchip: don't crash if we get an FDT we can't parse

When we parse the param from BL2, we try to parse it as a FDT and then,
if that fails, as aux params. However, we don't sufficiently distinguish
between failure modes in the first step: specifically, if we are given
an FDT with good magic that we can't parse for some other reason (e.g.
not enough space in our buffer), we still attempt to parse it as aux
params even though that's guaranteed to fatal. Instead, we should either
fail with a more descriptive message or continue to boot without parsing
the FDT.

This patch takes the latter approach, since all we currently get from
the FDT is non-critical UART params.

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: I1e98f1fcda4f78e6b45e86956288bafe58b113e4

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plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board

Add support for the iEi Puzzle-M801 board that is based on
the Marvell Armada 88F8040 SoC.

It supports 1 x 288-pin DIMM, DDR4 2400M

plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board

Add support for the iEi Puzzle-M801 board that is based on
the Marvell Armada 88F8040 SoC.

It supports 1 x 288-pin DIMM, DDR4 2400MHz up to 16 GB (ECC).

The iEi Puzzle-M801 board is using a custom MCU to handle board
power management. The MCU is managing the boards power LEDs, fans
and some other periferals. It's using UART for communication.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I0826ef8bf651b69aad5803184f20930ac7212ef8

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plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable

Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.

plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable

Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.

The variable was not updated, when it was deprecated in a8k_common.mk
in commit 613bbde09e48874658af5a00612fe2a0b0388523.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8

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Merge "arm_fpga: Fix MPIDR topology checks" into integration

Merge changes from topic "stm32-shres" into integration

* changes:
stm32mp1: shared resources: apply registered configuration
stm32mp1: shared resources: count GPIOZ bank pins
stm32mp1: shared

Merge changes from topic "stm32-shres" into integration

* changes:
stm32mp1: shared resources: apply registered configuration
stm32mp1: shared resources: count GPIOZ bank pins
stm32mp1: shared resources: define resource identifiers

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Merge "stm32mp1: introduce shared resources support" into integration