1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 27 ``aarch64``. 28 29- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 30 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 31 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 32 :ref:`Firmware Design`. 33 34- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 35 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 36 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 37 38- ``BL2``: This is an optional build option which specifies the path to BL2 39 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 40 built. 41 42- ``BL2U``: This is an optional build option which specifies the path to 43 BL2U image. In this case, the BL2U in TF-A will not be built. 44 45- ``BL2_AT_EL3``: This is an optional build option that enables the use of 46 BL2 at EL3 execution level. 47 48- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 49 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 50 the RW sections in RAM, while leaving the RO sections in place. This option 51 enable this use-case. For now, this option is only supported when BL2_AT_EL3 52 is set to '1'. 53 54- ``BL31``: This is an optional build option which specifies the path to 55 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 56 be built. 57 58- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 59 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 60 this file name will be used to save the key. 61 62- ``BL32``: This is an optional build option which specifies the path to 63 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 64 be built. 65 66- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 67 Trusted OS Extra1 image for the ``fip`` target. 68 69- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 70 Trusted OS Extra2 image for the ``fip`` target. 71 72- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 73 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 74 this file name will be used to save the key. 75 76- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 77 ``fip`` target in case TF-A BL2 is used. 78 79- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 80 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 81 this file name will be used to save the key. 82 83- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 84 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 85 If enabled, it is needed to use a compiler that supports the option 86 ``-mbranch-protection``. Selects the branch protection features to use: 87- 0: Default value turns off all types of branch protection 88- 1: Enables all types of branch protection features 89- 2: Return address signing to its standard level 90- 3: Extend the signing to include leaf functions 91- 4: Turn on branch target identification mechanism 92 93 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 94 and resulting PAuth/BTI features. 95 96 +-------+--------------+-------+-----+ 97 | Value | GCC option | PAuth | BTI | 98 +=======+==============+=======+=====+ 99 | 0 | none | N | N | 100 +-------+--------------+-------+-----+ 101 | 1 | standard | Y | Y | 102 +-------+--------------+-------+-----+ 103 | 2 | pac-ret | Y | N | 104 +-------+--------------+-------+-----+ 105 | 3 | pac-ret+leaf | Y | N | 106 +-------+--------------+-------+-----+ 107 | 4 | bti | N | Y | 108 +-------+--------------+-------+-----+ 109 110 This option defaults to 0 and this is an experimental feature. 111 Note that Pointer Authentication is enabled for Non-secure world 112 irrespective of the value of this option if the CPU supports it. 113 114- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 115 compilation of each build. It must be set to a C string (including quotes 116 where applicable). Defaults to a string that contains the time and date of 117 the compilation. 118 119- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 120 build to be uniquely identified. Defaults to the current git commit id. 121 122- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 123 124- ``CFLAGS``: Extra user options appended on the compiler's command line in 125 addition to the options set by the build system. 126 127- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 128 release several CPUs out of reset. It can take either 0 (several CPUs may be 129 brought up) or 1 (only one CPU will ever be brought up during cold reset). 130 Default is 0. If the platform always brings up a single CPU, there is no 131 need to distinguish between primary and secondary CPUs and the boot path can 132 be optimised. The ``plat_is_my_cpu_primary()`` and 133 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 134 to be implemented in this case. 135 136- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 137 Defaults to ``tbbr``. 138 139- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 140 register state when an unexpected exception occurs during execution of 141 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 142 this is only enabled for a debug build of the firmware. 143 144- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 145 certificate generation tool to create new keys in case no valid keys are 146 present or specified. Allowed options are '0' or '1'. Default is '1'. 147 148- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 149 the AArch32 system registers to be included when saving and restoring the 150 CPU context. The option must be set to 0 for AArch64-only platforms (that 151 is on hardware that does not implement AArch32, or at least not at EL1 and 152 higher ELs). Default value is 1. 153 154- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 155 operations when entering/exiting an EL2 execution context. This is of primary 156 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 157 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 158 ``SPMD_SPM_AT_SEL2`` is set. 159 160- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 161 registers to be included when saving and restoring the CPU context. Default 162 is 0. 163 164- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 165 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 166 registers to be included when saving and restoring the CPU context as 167 part of world switch. Default value is 0 and this is an experimental feature. 168 Note that Pointer Authentication is enabled for Non-secure world irrespective 169 of the value of this flag if the CPU supports it. 170 171- ``DEBUG``: Chooses between a debug and release build. It can take either 0 172 (release) or 1 (debug) as values. 0 is the default. 173 174- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 175 authenticated decryption algorithm to be used to decrypt firmware/s during 176 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 177 this flag is ``none`` to disable firmware decryption which is an optional 178 feature as per TBBR. Also, it is an experimental feature. 179 180- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 181 of the binary image. If set to 1, then only the ELF image is built. 182 0 is the default. 183 184- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 185 Board Boot authentication at runtime. This option is meant to be enabled only 186 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 187 flag has to be enabled. 0 is the default. 188 189- ``E``: Boolean option to make warnings into errors. Default is 1. 190 191- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 192 the normal boot flow. It must specify the entry point address of the EL3 193 payload. Please refer to the "Booting an EL3 payload" section for more 194 details. 195 196- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 197 This is an optional architectural feature available on v8.4 onwards. Some 198 v8.2 implementations also implement an AMU and this option can be used to 199 enable this feature on those systems as well. Default is 0. 200 201- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 202 are compiled out. For debug builds, this option defaults to 1, and calls to 203 ``assert()`` are left in place. For release builds, this option defaults to 0 204 and calls to ``assert()`` function are compiled out. This option can be set 205 independently of ``DEBUG``. It can also be used to hide any auxiliary code 206 that is only required for the assertion and does not fit in the assertion 207 itself. 208 209- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 210 dumps or not. It is supported in both AArch64 and AArch32. However, in 211 AArch32 the format of the frame records are not defined in the AAPCS and they 212 are defined by the implementation. This implementation of backtrace only 213 supports the format used by GCC when T32 interworking is disabled. For this 214 reason enabling this option in AArch32 will force the compiler to only 215 generate A32 code. This option is enabled by default only in AArch64 debug 216 builds, but this behaviour can be overridden in each platform's Makefile or 217 in the build command line. 218 219- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 220 support in GCC for TF-A. This option is currently only supported for 221 AArch64. Default is 0. 222 223- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 224 feature. MPAM is an optional Armv8.4 extension that enables various memory 225 system components and resources to define partitions; software running at 226 various ELs can assign themselves to desired partition to control their 227 performance aspects. 228 229 When this option is set to ``1``, EL3 allows lower ELs to access their own 230 MPAM registers without trapping into EL3. This option doesn't make use of 231 partitioning in EL3, however. Platform initialisation code should configure 232 and use partitions in EL3 as required. This option defaults to ``0``. 233 234- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 235 support within generic code in TF-A. This option is currently only supported 236 in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. 237 238- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 239 Measurement Framework(PMF). Default is 0. 240 241- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 242 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 243 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 244 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 245 software. 246 247- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 248 instrumentation which injects timestamp collection points into TF-A to 249 allow runtime performance to be measured. Currently, only PSCI is 250 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 251 as well. Default is 0. 252 253- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 254 extensions. This is an optional architectural feature for AArch64. 255 The default is 1 but is automatically disabled when the target architecture 256 is AArch32. 257 258- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 259 (SVE) for the Non-secure world only. SVE is an optional architectural feature 260 for AArch64. Note that when SVE is enabled for the Non-secure world, access 261 to SIMD and floating-point functionality from the Secure world is disabled. 262 This is to avoid corruption of the Non-secure world data in the Z-registers 263 which are aliased by the SIMD and FP registers. The build option is not 264 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 265 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 266 1. The default is 1 but is automatically disabled when the target 267 architecture is AArch32. 268 269- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 270 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 271 default value is set to "none". "strong" is the recommended stack protection 272 level if this feature is desired. "none" disables the stack protection. For 273 all values other than "none", the ``plat_get_stack_protector_canary()`` 274 platform hook needs to be implemented. The value is passed as the last 275 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 276 277- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 278 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 279 experimental. 280 281- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 282 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 283 experimental. 284 285- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 286 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 287 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental. 288 289- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 290 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 291 build flag which is marked as experimental. 292 293- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 294 deprecated platform APIs, helper functions or drivers within Trusted 295 Firmware as error. It can take the value 1 (flag the use of deprecated 296 APIs as error) or 0. The default is 0. 297 298- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 299 targeted at EL3. When set ``0`` (default), no exceptions are expected or 300 handled at EL3, and a panic will result. This is supported only for AArch64 301 builds. 302 303- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 304 injection from lower ELs, and this build option enables lower ELs to use 305 Error Records accessed via System Registers to inject faults. This is 306 applicable only to AArch64 builds. 307 308 This feature is intended for testing purposes only, and is advisable to keep 309 disabled for production images. 310 311- ``FIP_NAME``: This is an optional build option which specifies the FIP 312 filename for the ``fip`` target. Default is ``fip.bin``. 313 314- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 315 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 316 317- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 318 319 :: 320 321 0: Encryption is done with Secret Symmetric Key (SSK) which is common 322 for a class of devices. 323 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 324 unique per device. 325 326 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 327 experimental. 328 329- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 330 tool to create certificates as per the Chain of Trust described in 331 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 332 include the certificates in the FIP and FWU_FIP. Default value is '0'. 333 334 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 335 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 336 the corresponding certificates, and to include those certificates in the 337 FIP and FWU_FIP. 338 339 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 340 images will not include support for Trusted Board Boot. The FIP will still 341 include the corresponding certificates. This FIP can be used to verify the 342 Chain of Trust on the host machine through other mechanisms. 343 344 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 345 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 346 will not include the corresponding certificates, causing a boot failure. 347 348- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 349 inherent support for specific EL3 type interrupts. Setting this build option 350 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 351 by `platform abstraction layer`__ and `Interrupt Management Framework`__. 352 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 353 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 354 the Secure Payload interrupts needs to be synchronously handed over to Secure 355 EL1 for handling. The default value of this option is ``0``, which means the 356 Group 0 interrupts are assumed to be handled by Secure EL1. 357 358 .. __: platform-interrupt-controller-API.rst 359 .. __: interrupt-framework-design.rst 360 361- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 362 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 363 ``0`` (default), these exceptions will be trapped in the current exception 364 level (or in EL1 if the current exception level is EL0). 365 366- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 367 software operations are required for CPUs to enter and exit coherency. 368 However, newer systems exist where CPUs' entry to and exit from coherency 369 is managed in hardware. Such systems require software to only initiate these 370 operations, and the rest is managed in hardware, minimizing active software 371 management. In such systems, this boolean option enables TF-A to carry out 372 build and run-time optimizations during boot and power management operations. 373 This option defaults to 0 and if it is enabled, then it implies 374 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 375 376 If this flag is disabled while the platform which TF-A is compiled for 377 includes cores that manage coherency in hardware, then a compilation error is 378 generated. This is based on the fact that a system cannot have, at the same 379 time, cores that manage coherency in hardware and cores that don't. In other 380 words, a platform cannot have, at the same time, cores that require 381 ``HW_ASSISTED_COHERENCY=1`` and cores that require 382 ``HW_ASSISTED_COHERENCY=0``. 383 384 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 385 translation library (xlat tables v2) must be used; version 1 of translation 386 library is not supported. 387 388- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 389 bottom, higher addresses at the top. This buid flag can be set to '1' to 390 invert this behavior. Lower addresses will be printed at the top and higher 391 addresses at the bottom. 392 393- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 394 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 395 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 396 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 397 images. 398 399- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 400 used for generating the PKCS keys and subsequent signing of the certificate. 401 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 402 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 403 compliant and is retained only for compatibility. The default value of this 404 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 405 406- ``KEY_SIZE``: This build flag enables the user to select the key size for 407 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 408 depend on the chosen algorithm and the cryptographic module. 409 410 +-----------+------------------------------------+ 411 | KEY_ALG | Possible key sizes | 412 +===========+====================================+ 413 | rsa | 1024 , 2048 (default), 3072, 4096* | 414 +-----------+------------------------------------+ 415 | ecdsa | unavailable | 416 +-----------+------------------------------------+ 417 418 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 419 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 420 421- ``HASH_ALG``: This build flag enables the user to select the secure hash 422 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 423 The default value of this flag is ``sha256``. 424 425- ``LDFLAGS``: Extra user options appended to the linkers' command line in 426 addition to the one set by the build system. 427 428- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 429 output compiled into the build. This should be one of the following: 430 431 :: 432 433 0 (LOG_LEVEL_NONE) 434 10 (LOG_LEVEL_ERROR) 435 20 (LOG_LEVEL_NOTICE) 436 30 (LOG_LEVEL_WARNING) 437 40 (LOG_LEVEL_INFO) 438 50 (LOG_LEVEL_VERBOSE) 439 440 All log output up to and including the selected log level is compiled into 441 the build. The default value is 40 in debug builds and 20 in release builds. 442 443- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 444 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set. 445 This option defaults to 0 and is an experimental feature in the stage of 446 development. 447 448- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 449 specifies the file that contains the Non-Trusted World private key in PEM 450 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 451 452- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 453 optional. It is only needed if the platform makefile specifies that it 454 is required in order to build the ``fwu_fip`` target. 455 456- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 457 contents upon world switch. It can take either 0 (don't save and restore) or 458 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 459 wants the timer registers to be saved and restored. 460 461- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 462 for the BL image. It can be either 0 (include) or 1 (remove). The default 463 value is 0. 464 465- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 466 the underlying hardware is not a full PL011 UART but a minimally compliant 467 generic UART, which is a subset of the PL011. The driver will not access 468 any register that is not part of the SBSA generic UART specification. 469 Default value is 0 (a full PL011 compliant UART is present). 470 471- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 472 must be subdirectory of any depth under ``plat/``, and must contain a 473 platform makefile named ``platform.mk``. For example, to build TF-A for the 474 Arm Juno board, select PLAT=juno. 475 476- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 477 instead of the normal boot flow. When defined, it must specify the entry 478 point address for the preloaded BL33 image. This option is incompatible with 479 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 480 over ``PRELOADED_BL33_BASE``. 481 482- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 483 vector address can be programmed or is fixed on the platform. It can take 484 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 485 programmable reset address, it is expected that a CPU will start executing 486 code directly at the right address, both on a cold and warm reset. In this 487 case, there is no need to identify the entrypoint on boot and the boot path 488 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 489 does not need to be implemented in this case. 490 491- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 492 possible for the PSCI power-state parameter: original and extended State-ID 493 formats. This flag if set to 1, configures the generic PSCI layer to use the 494 extended format. The default value of this flag is 0, which means by default 495 the original power-state format is used by the PSCI implementation. This flag 496 should be specified by the platform makefile and it governs the return value 497 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 498 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 499 set to 1 as well. 500 501- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 502 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 503 or later CPUs. 504 505 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 506 set to ``1``. 507 508 This option is disabled by default. 509 510- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 511 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 512 entrypoint) or 1 (CPU reset to BL31 entrypoint). 513 The default value is 0. 514 515- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 516 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 517 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 518 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 519 520- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 521 file that contains the ROT private key in PEM format and enforces public key 522 hash generation. If ``SAVE_KEYS=1``, this 523 file name will be used to save the key. 524 525- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 526 certificate generation tool to save the keys used to establish the Chain of 527 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 528 529- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 530 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 531 target. 532 533- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 534 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 535 this file name will be used to save the key. 536 537- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 538 optional. It is only needed if the platform makefile specifies that it 539 is required in order to build the ``fwu_fip`` target. 540 541- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 542 Delegated Exception Interface to BL31 image. This defaults to ``0``. 543 544 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 545 set to ``1``. 546 547- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 548 isolated on separate memory pages. This is a trade-off between security and 549 memory usage. See "Isolating code and read-only data on separate memory 550 pages" section in :ref:`Firmware Design`. This flag is disabled by default 551 and affects all BL images. 552 553- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 554 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 555 allocated in RAM discontiguous from the loaded firmware image. When set, the 556 platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and 557 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 558 sections are placed in RAM immediately following the loaded firmware image. 559 560- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 561 This build option is only valid if ``ARCH=aarch64``. The value should be 562 the path to the directory containing the SPD source, relative to 563 ``services/spd/``; the directory is expected to contain a makefile called 564 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 565 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 566 cannot be enabled when the ``SPM_MM`` option is enabled. 567 568- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 569 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 570 execution in BL1 just before handing over to BL31. At this point, all 571 firmware images have been loaded in memory, and the MMU and caches are 572 turned off. Refer to the "Debugging options" section for more details. 573 574- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 575 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 576 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 577 extension. This is the default when enabling the SPM Dispatcher. When 578 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 579 state. This latter configuration supports pre-Armv8.4 platforms (aka not 580 implementing the Armv8.4-SecEL2 extension). 581 582- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 583 Partition Manager (SPM) implementation. The default value is ``0`` 584 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 585 enabled (``SPD=spmd``). 586 587- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 588 description of secure partitions. The build system will parse this file and 589 package all secure partition blobs into the FIP. This file is not 590 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 591 592- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 593 secure interrupts (caught through the FIQ line). Platforms can enable 594 this directive if they need to handle such interruption. When enabled, 595 the FIQ are handled in monitor mode and non secure world is not allowed 596 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 597 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 598 599- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 600 Boot feature. When set to '1', BL1 and BL2 images include support to load 601 and verify the certificates and images in a FIP, and BL1 includes support 602 for the Firmware Update. The default value is '0'. Generation and inclusion 603 of certificates in the FIP and FWU_FIP depends upon the value of the 604 ``GENERATE_COT`` option. 605 606 .. warning:: 607 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 608 already exist in disk, they will be overwritten without further notice. 609 610- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 611 specifies the file that contains the Trusted World private key in PEM 612 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 613 614- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 615 synchronous, (see "Initializing a BL32 Image" section in 616 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 617 synchronous method) or 1 (BL32 is initialized using asynchronous method). 618 Default is 0. 619 620- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 621 routing model which routes non-secure interrupts asynchronously from TSP 622 to EL3 causing immediate preemption of TSP. The EL3 is responsible 623 for saving and restoring the TSP context in this routing model. The 624 default routing model (when the value is 0) is to route non-secure 625 interrupts to TSP allowing it to save its context and hand over 626 synchronously to EL3 via an SMC. 627 628 .. note:: 629 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 630 must also be set to ``1``. 631 632- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 633 linker. When the ``LINKER`` build variable points to the armlink linker, 634 this flag is enabled automatically. To enable support for armlink, platforms 635 will have to provide a scatter file for the BL image. Currently, Tegra 636 platforms use the armlink support to compile BL3-1 images. 637 638- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 639 memory region in the BL memory map or not (see "Use of Coherent memory in 640 TF-A" section in :ref:`Firmware Design`). It can take the value 1 641 (Coherent memory region is included) or 0 (Coherent memory region is 642 excluded). Default is 1. 643 644- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 645 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 646 Default is 0. 647 648- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 649 firmware configuration framework. This will move the io_policies into a 650 configuration device tree, instead of static structure in the code base. 651 This is currently an experimental feature. 652 653- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 654 at runtime using fconf. If this flag is enabled, COT descriptors are 655 statically captured in tb_fw_config file in the form of device tree nodes 656 and properties. Currently, COT descriptors used by BL2 are moved to the 657 device tree and COT descriptors used by BL1 are retained in the code 658 base statically. This is currently an experimental feature. 659 660- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 661 runtime using firmware configuration framework. The platform specific SDEI 662 shared and private events configuration is retrieved from device tree rather 663 than static C structures at compile time. This is currently an experimental 664 feature and is only supported if SDEI_SUPPORT build flag is enabled. 665 666- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 667 and Group1 secure interrupts using the firmware configuration framework. The 668 platform specific secure interrupt property descriptor is retrieved from 669 device tree in runtime rather than depending on static C structure at compile 670 time. This is currently an experimental feature. 671 672- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 673 This feature creates a library of functions to be placed in ROM and thus 674 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 675 is 0. 676 677- ``V``: Verbose build. If assigned anything other than 0, the build commands 678 are printed. Default is 0. 679 680- ``VERSION_STRING``: String used in the log output for each TF-A image. 681 Defaults to a string formed by concatenating the version number, build type 682 and build string. 683 684- ``W``: Warning level. Some compiler warning options of interest have been 685 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 686 each level enabling more warning options. Default is 0. 687 688- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 689 the CPU after warm boot. This is applicable for platforms which do not 690 require interconnect programming to enable cache coherency (eg: single 691 cluster platforms). If this option is enabled, then warm boot path 692 enables D-caches immediately after enabling MMU. This option defaults to 0. 693 694- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 695 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 696 default value of this flag is ``no``. Note this option must be enabled only 697 for ARM architecture greater than Armv8.5-A. 698 699- ``ERRATA_SPECULATIVE_AT``: This flag enables/disables page table walk during 700 context restore as speculative AT instructions using an out-of-context 701 translation regime could cause subsequent requests to generate an incorrect 702 translation. 703 System registers are not updated during context save, hence this workaround 704 need not be applied in the context save path. 705 706 This boolean option enables errata for all below CPUs. 707 708 +---------+--------------+ 709 | Errata | CPU | 710 +=========+==============+ 711 | 1165522 | Cortex-A76 | 712 +---------+--------------+ 713 | 1319367 | Cortex-A72 | 714 +---------+--------------+ 715 | 1319537 | Cortex-A57 | 716 +---------+--------------+ 717 | 1530923 | Cortex-A55 | 718 +---------+--------------+ 719 | 1530924 | Cortex-A53 | 720 +---------+--------------+ 721 722- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 723 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 724 This flag is disabled by default. 725 726- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 727 path on the host machine which is used to build certificate generation and 728 firmware encryption tool. 729 730GICv3 driver options 731-------------------- 732 733GICv3 driver files are included using directive: 734 735``include drivers/arm/gic/v3/gicv3.mk`` 736 737The driver can be configured with the following options set in the platform 738makefile: 739 740- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 741 Enabling this option will add runtime detection support for the 742 GIC-600, so is safe to select even for a GIC500 implementation. 743 This option defaults to 0. 744 745- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 746 functionality. This option defaults to 0 747 748- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 749 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 750 functions. This is required for FVP platform which need to simulate GIC save 751 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 752 753- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 754 This option defaults to 0. 755 756- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 757 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 758 759Debugging options 760----------------- 761 762To compile a debug version and make the build more verbose use 763 764.. code:: shell 765 766 make PLAT=<platform> DEBUG=1 V=1 all 767 768AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 769example DS-5) might not support this and may need an older version of DWARF 770symbols to be emitted by GCC. This can be achieved by using the 771``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 772version to 2 is recommended for DS-5 versions older than 5.16. 773 774When debugging logic problems it might also be useful to disable all compiler 775optimizations by using ``-O0``. 776 777.. warning:: 778 Using ``-O0`` could cause output images to be larger and base addresses 779 might need to be recalculated (see the **Memory layout on Arm development 780 platforms** section in the :ref:`Firmware Design`). 781 782Extra debug options can be passed to the build system by setting ``CFLAGS`` or 783``LDFLAGS``: 784 785.. code:: shell 786 787 CFLAGS='-O0 -gdwarf-2' \ 788 make PLAT=<platform> DEBUG=1 V=1 all 789 790Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 791ignored as the linker is called directly. 792 793It is also possible to introduce an infinite loop to help in debugging the 794post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 795``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 796section. In this case, the developer may take control of the target using a 797debugger when indicated by the console output. When using DS-5, the following 798commands can be used: 799 800:: 801 802 # Stop target execution 803 interrupt 804 805 # 806 # Prepare your debugging environment, e.g. set breakpoints 807 # 808 809 # Jump over the debug loop 810 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 811 812 # Resume execution 813 continue 814 815-------------- 816 817*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 818