Merge "mediatek: move uart.h to common folder" into integration

Add SiP service to configure Arm Ethos-N NPU

By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still

Add SiP service to configure Arm Ethos-N NPU

By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still allow the non-secure world to use the NPU, a SiP service has
been added that can delegate non-secure access to the registers needed
to use it.

Only the HW_CONFIG for the Arm Juno platform has been updated to include
the device tree for the NPU and the platform currently only loads the
HW_CONFIG in AArch64 builds.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2

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plat/arm/juno: Add support to use hw_config in BL31

To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been

plat/arm/juno: Add support to use hw_config in BL31

To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been added that is included in the FIP and a Juno specific BL31
setup has been added to populate fconf with the hw_config.

Juno's BL2 setup has been updated to align it with the new behavior
implemented in the Arm FVP platform, where fw_config is passed in arg1
to BL31 instead of soc_fw_config. The BL31 setup is expected to use the
fw_config passed in arg1 to find the hw_config.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6

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plat/marvell: remove subversion from Marvell make files

Subversion is not reflecting the Marvell sources variant anymore.
This patch removes version.mk from Marvell plafroms.

Signed-off-by: Konstan

plat/marvell: remove subversion from Marvell make files

Subversion is not reflecting the Marvell sources variant anymore.
This patch removes version.mk from Marvell plafroms.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I8f3afbe3fab3a38da68876f77455f449f5fe0179

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plat/marvell: a8k: move efuse definitions to separate header

Move efuse definitions to a separate header file for later
usage with other FW modules.

Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2

plat/marvell: a8k: move efuse definitions to separate header

Move efuse definitions to a separate header file for later
usage with other FW modules.

Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>

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plat/marvell/armada: fix TRNG return SMC handling

Use single 64b register for the return value instead of two 32b.
Report an error if caller requested larger than than 64b random
number in a single

plat/marvell/armada: fix TRNG return SMC handling

Use single 64b register for the return value instead of two 32b.
Report an error if caller requested larger than than 64b random
number in a single SMC call.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Ib8756cd3c0808b78c359f90c6f6913f7d16ac360
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/33280
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

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drivers: marvell: comphy: add rx training on 10G port

This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.

Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Ie

drivers: marvell: comphy: add rx training on 10G port

This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.

Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

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plat/marvell/armada: postpone MSS CPU startup to BL31 stage

Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes s

plat/marvell/armada: postpone MSS CPU startup to BL31 stage

Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes should be
changed from defaults before the MSS CPU tries to access shared resources.
This patch starts to use CP MSS SRAM for FW load in both secure and
non-secure boot modes.
The FW loader inserts a magic number into MSS SRAM as an indicator of
successfully loaded FS during the BL2 stage and skips releasing the MSS
CPU from the reset state.
Then, at BL31 stage, the MSS CPU is released from reset following the
call to cp110_init function that handles all the required bus attributes
configurations.

Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

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plat: marvell: armada: a8k: Fix LD selector mask

Fixed a bug that the actually bit number was used as a mask to
select LD0 or LD1 fuse

Signed-off-by: Guo Yi <yguo@cavium.com>
Change-Id: I4bec268c3d

plat: marvell: armada: a8k: Fix LD selector mask

Fixed a bug that the actually bit number was used as a mask to
select LD0 or LD1 fuse

Signed-off-by: Guo Yi <yguo@cavium.com>
Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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plat/marvell/armada: allow builds without MSS support

Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and w

plat/marvell/armada: allow builds without MSS support

Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and will not support PM, FC and other features implemented
in these FW images.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

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drivers: marvell: add support for secure read/write of dfx register-set

Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In intr

drivers: marvell: add support for secure read/write of dfx register-set

Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.

This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.

Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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ddr_phy: use smc calls to access ddr phy registers

Added smc calls support to access ddr phy registers.

Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@mar

ddr_phy: use smc calls to access ddr phy registers

Added smc calls support to access ddr phy registers.

Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20791
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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drivers: marvell: thermal: use dedicated function for thermal SiPs

Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name

drivers: marvell: thermal: use dedicated function for thermal SiPs

Since more drivers which uses dfx register set need to be handled with
use of SiP services, use dedicated and more meaningful name for thermal
SiP services.

Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25054
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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drivers: marvell: add thermal sensor driver and expose it via SIP service

Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), acce

drivers: marvell: add thermal sensor driver and expose it via SIP service

Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), accessing thermal
registers which are part of dfx register set, will not be possible from
lower exception levels. Due to above expose thermal driver as a SiP
service. This will allow Linux and U-Boot thermal driver to initialise
and perform various operations on thermal sensor.

The thermal sensor driver is based on Linux
drivers/thermal/armada_thermal.c.

Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/20581
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>

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fix: plat: marvell: fix MSS loader for A8K family

Wrong brakets caused MSS FW load timeout error:
ERROR: MSS DMA failed (timeout)
ERROR: MSS FW chunk 0 load failed
ERROR: SCP Image load failed

fix: plat: marvell: fix MSS loader for A8K family

Wrong brakets caused MSS FW load timeout error:
ERROR: MSS DMA failed (timeout)
ERROR: MSS FW chunk 0 load failed
ERROR: SCP Image load failed

This patch fixes the operator precedence in MSS FW load.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I78c215606bde112f40429926c51f5fa1e4334c13

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mediatek: mt8192: devapc: Add devapc driver

Add devapc driver for setting default permission.

Change-Id: I103f27ae090fbed76ce9319606ac082d78b74566
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>

Arm: Fix error message printing in board makefile

Remove an incorrect tabulation in front of an $(error) function call
outside of a recipe, which caused the following text to be displayed:

plat/a

Arm: Fix error message printing in board makefile

Remove an incorrect tabulation in front of an $(error) function call
outside of a recipe, which caused the following text to be displayed:

plat/arm/board/common/board_common.mk:36: *** recipe commences before first target. Stop.

instead of:

plat/arm/board/common/board_common.mk:36: *** "Unsupported ARM_ROTPK_LOCATION value". Stop.

Change-Id: I8592948e7de8ab0c4abbc56eb65a53eb1875a83c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge changes from topic "scmi_v2_0" into integration

* changes:
drivers/arm/css/scmi: Update power domain protocol version to 2.0
tc0: update GICR base address

mediatek: move uart.h to common folder

UART register definition is the same on MediaTek platforms.
Move uart.h to common folder and remove the duplicate file.

Signed-off-by: Yidi Lin <yidi.lin@medi

mediatek: move uart.h to common folder

UART register definition is the same on MediaTek platforms.
Move uart.h to common folder and remove the duplicate file.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iea0931dfd606ae4a7ab475b9cb3a08dc6de68b36

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tc0: update GICR base address

The number of ITS have changed from 4 to 1, resulting
in GICR base address change.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642

tc0: update GICR base address

The number of ITS have changed from 4 to 1, resulting
in GICR base address change.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7

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Merge changes from topic "dcc_console" into integration

* changes:
plat:xilinx:versal: Add JTAG DCC support
plat:xilinx:zynqmp: Add JTAG DCC support
drivers: dcc: Support JTAG DCC console

Merge "plat/arm: don't provide NT_FW_CONFIG when booting hafnium" into integration

plat/qemu: add "max" cpu support

Add support to qemu "max" cpu for both "qemu" ('virt') and
"qemu_sbsa" ('sbsa-ref') platforms.

Change-Id: I36e45c0a3c4e30ba546d2a3cb44dfef11a680305
Signed-off-by: L

plat/qemu: add "max" cpu support

Add support to qemu "max" cpu for both "qemu" ('virt') and
"qemu_sbsa" ('sbsa-ref') platforms.

Change-Id: I36e45c0a3c4e30ba546d2a3cb44dfef11a680305
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

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plat/qemu: add cortex-a72 support to 'virt' platform

Cortex-A72 support is already enabled for sbsa-ref platform,
so add it also to virt platform for parity.

Change-Id: Ib0a2ce81ef7c0a71ef8dc66dbec

plat/qemu: add cortex-a72 support to 'virt' platform

Cortex-A72 support is already enabled for sbsa-ref platform,
so add it also to virt platform for parity.

Change-Id: Ib0a2ce81ef7c0a71ef8dc66dbec179191bf2e6cc
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

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plat/qemu: include gicv2.mk

The build now gives deprecation warnings for including
drivers/arm/gic/common/gic_common.c directly. Move to including the
common gicv2 sources via gicv2.mk instead - whi

plat/qemu: include gicv2.mk

The build now gives deprecation warnings for including
drivers/arm/gic/common/gic_common.c directly. Move to including the
common gicv2 sources via gicv2.mk instead - which also matches the
pattern already used for gicv3.

Change-Id: I5332fb52c5801272e5e2bb6111f96087b4894325
Signed-off-by: Leif Lindholm <leif@nuviainc.com>

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