| dd4268a2 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: psci platform functions used by lib/psci
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9853263ed38fb2a9f04b9dc7d768942e32074719 |
| 044ddf9e | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: helper function used by plat & common code
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Idafd8b0d94edf3515e8317431274d77289b7a1d0 |
| bdfad087 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: add data handler used by bl31
bl31-data file written in assembly helps to manage data at bl31.
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Cha
nxp: add data handler used by bl31
bl31-data file written in assembly helps to manage data at bl31.
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic3ace03364648cc1174bb05b5b334b9ccdaaa4ed
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|
| de37db6c | 24-Jan-2021 |
Samuel Holland <samuel@sholland.org> |
allwinner: Use CPUIDLE hardware when available
This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.
Change-Id: I9f2fed597189bb387de7
allwinner: Use CPUIDLE hardware when available
This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.
Change-Id: I9f2fed597189bb387de79e8e76a7da3375e1ee91
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|
| ad329e50 | 21-Dec-2020 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
plat: imx8mm: Add in BL2 with FIP
Adds bl2 with FIP to the build required for mbed Linux booting where
we do:
BootROM -> SPL -> BL2 -> OPTEE -> u-boot
If NEED_BL2 is specified then BL2 will be bui
plat: imx8mm: Add in BL2 with FIP
Adds bl2 with FIP to the build required for mbed Linux booting where
we do:
BootROM -> SPL -> BL2 -> OPTEE -> u-boot
If NEED_BL2 is specified then BL2 will be built and BL31 will have
its address range modified upwards to accommodate. BL31 must be
loaded from a FIP in this case.
If NEED_BL2 is not specified then the current BL31 boot flow is
unaffected and u-boot SPL will load and execute BL31 directly.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I655343b3b689b1fc57cfbedda4d3dc2fbd549a96
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|
| e364a8c3 | 17-Apr-2019 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
plat: imx8mm: Add image load logic for TBBR FIP booting
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I0557ce6d0
plat: imx8mm: Add image load logic for TBBR FIP booting
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I0557ce6d0aa5ab321cac1ee25280b96762024396
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|
| f255cad7 | 21-Dec-2020 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
plat: imx8mm: Enable Trusted Boot
This patch enables Trusted Boot on the i.MX8MM with BL2 doing image
verification from a FIP prior to hand-over to BL31.
Signed-off-by: Bryan O'Donoghue <bryan.odon
plat: imx8mm: Enable Trusted Boot
This patch enables Trusted Boot on the i.MX8MM with BL2 doing image
verification from a FIP prior to hand-over to BL31.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I3c22783a5c49544d0bace8ef3724784b9b7cc64a
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|
| 37ac9b7f | 30-May-2019 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
plat: imx8mm: Add initial defintions to facilitate FIP layout
Adds a number of definitions consistent with the established WaRP7
equivalents specifying number of io_handles and block devices.
Signe
plat: imx8mm: Add initial defintions to facilitate FIP layout
Adds a number of definitions consistent with the established WaRP7
equivalents specifying number of io_handles and block devices.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: If1d7ef1ad3ac3dfc860f949392c7534ce8d206e3
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|
| ee4d094a | 17-Apr-2019 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
plat: imx8mm: Add image io-storage logic for TBBR FIP booting
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I983
plat: imx8mm: Add image io-storage logic for TBBR FIP booting
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I9833a54d0938d70886ac88b1922b17edf1dee8e0
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|
| 1329f964 | 23-Apr-2019 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
plat: imx8mm: Add imx8mm_private.h to the build
Allows for exporting of FIP related methods cleanly in a private header.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by:
plat: imx8mm: Add imx8mm_private.h to the build
Allows for exporting of FIP related methods cleanly in a private header.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I8523f1370312ed22ff7ca710cd916be52f725e3c
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|
| 236fc428 | 25-Apr-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add TZC400 interrupt management
TZC400 is configured to raise an interrupt in case of faulty access.
Call the new added tzc400_it_handler, in case this interrupt occurs.
Change-Id: Iaf4fa
stm32mp1: add TZC400 interrupt management
TZC400 is configured to raise an interrupt in case of faulty access.
Call the new added tzc400_it_handler, in case this interrupt occurs.
Change-Id: Iaf4fa408a8eff99498042e11e2d6177bad39868c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| 1e80c498 | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: use TZC400 macro to describe filters
On STM32MP15, only filters 0 and 1 are used.
Use TZC_400_REGION_ATTR_FILTER_BIT() macro for those 2 filters 0 and 1
instead of U(3).
Change-Id: Ibc618
stm32mp1: use TZC400 macro to describe filters
On STM32MP15, only filters 0 and 1 are used.
Use TZC_400_REGION_ATTR_FILTER_BIT() macro for those 2 filters 0 and 1
instead of U(3).
Change-Id: Ibc61823842ade680f59d5b66b8db59b6a30080e4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| 830c7657 | 22-Mar-2021 |
Jan Kiszka <jan.kiszka@siemens.com> |
rpi4: Switch to gicv2.mk and GICV2_SOURCES
Addresses the deprecation warning produced by
drivers/arm/gic/common/gic_common.c.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I1a3ff483
rpi4: Switch to gicv2.mk and GICV2_SOURCES
Addresses the deprecation warning produced by
drivers/arm/gic/common/gic_common.c.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I1a3ff4835d0f94c74b405db10622e99875ded82b
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|
| 4697164a | 26-Feb-2021 |
Tejas Patel <tejas.patel@xilinx.com> |
plat: xilinx: versal: Mark IPI calls secure/non-secure
BIT24 of IPI command header is used to determine if caller is
secure or non-secure.
Mark BIT24 of IPI command header as non-secure if SMC call
plat: xilinx: versal: Mark IPI calls secure/non-secure
BIT24 of IPI command header is used to determine if caller is
secure or non-secure.
Mark BIT24 of IPI command header as non-secure if SMC caller
is non-secure.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267
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|
| 0888fcf2 | 18-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat: xilinx: versal: Remove cortex-a53 compilation" into integration |
| 0fb73638 | 18-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat: xilinx: Add timeout while waiting for IPI Ack" into integration |
| ae030052 | 16-Mar-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "od/ffa_spmc_pwr" into integration
* changes:
SPM: declare third cactus instance as UP SP
SPMD: lock the g_spmd_pm structure
FF-A: implement FFA_SECONDARY_EP_REGISTER |
| 4a7b060b | 16-Mar-2021 |
Michal Simek <michal.simek@xilinx.com> |
plat: xilinx: versal: Remove cortex-a53 compilation
Versal is a72 based that's why there is no reason to build low level
assemble code for a53.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
plat: xilinx: versal: Remove cortex-a53 compilation
Versal is a72 based that's why there is no reason to build low level
assemble code for a53.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6
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|
| 332649da | 15-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "matterhorn_elp" into integration
* changes:
plat: tc0: add matterhorn_elp_arm library to tc0
cpus: add Matterhorn ELP ARM cpu library |
| e96fc8e7 | 11-Feb-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many
SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
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|
| 5491208a | 12-Mar-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "linux_as_bl33" into integration
* changes:
plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31
plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33 |
| 72bdcb9a | 29-Jan-2021 |
Usama Arif <usama.arif@arm.com> |
plat: tc0: add matterhorn_elp_arm library to tc0
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: Ie199c60553477c43d1665548ae78cdfd1aa7ffcf |
| a8fb76e5 | 10-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I9c9ed516,I2788eaf6 into integration
* changes:
qemu/qemu_sbsa: fix memory type of secure NOR flash
qemu/qemu_sbsa: spm_mm supports 512 cores |
| ce19ac90 | 10-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices" into integration |
| 682fe370 | 24-Sep-2020 |
Bharat Gooty <bharat.gooty@broadcom.com> |
driver: brcm: add USB driver
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I456aa7a641fffa8ea4e833615af3effec42a31b2 |