feat(qemu): add A76/N1 cpu support for virt

Add support to "cortex-a76" and "neoverse-n1" cpu for "qemu" ('virt')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I77a3e0bb

feat(qemu): add A76/N1 cpu support for virt

Add support to "cortex-a76" and "neoverse-n1" cpu for "qemu" ('virt')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I77a3e0bb8397a2fb45a2caa7d93ba38e39297f93

show more ...

Merge "fix(tc): unify TC ROM start addresses" into integration

Merge "test(tc): test for AP/RSS NV counter interface" into integration

feat(st): mandate dtc version 1.4.7

To be able to use /omit-if-no-ref/ in DT files, the dtc version should
be at least 1.4.7. Update the makefile rule that checks dtc version.

Signed-off-by: Yann G

feat(st): mandate dtc version 1.4.7

To be able to use /omit-if-no-ref/ in DT files, the dtc version should
be at least 1.4.7. Update the makefile rule that checks dtc version.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I06bde289cf359a7383694e4c86991dfba781e7d7

show more ...

refactor(st): move mbedtls config files

The files stm32mp_mbedtls_config-{2,3}.h are moved to
plat/st/common/include directory as they could be shared with other ST
platforms. Their prefixes are cha

refactor(st): move mbedtls config files

The files stm32mp_mbedtls_config-{2,3}.h are moved to
plat/st/common/include directory as they could be shared with other ST
platforms. Their prefixes are changed from stm32mp1 to stm32mp.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I86e39481b6c8d2689c59eb9a351b77b3d6233b08

show more ...

refactor(st): add common mk files

Group configuration that could be common to several ST platforms.
Two common makefiles are created: common.mk for definitions and files
to compile, and common_rules

refactor(st): add common mk files

Group configuration that could be common to several ST platforms.
Two common makefiles are created: common.mk for definitions and files
to compile, and common_rules.mk that gathers makefile compilation rules.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7ea9b75c78e7d916854cdd984bbf921b1a46ebc4

show more ...

Merge "feat(morello): implement methods to retrieve soc-id information" into integration

Merge "fix(versal_net): fix irq for IPI0" into integration

Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).

BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.

Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

show more ...

feat(morello): implement methods to retrieve soc-id information

Added silicon revision in the platform information SDS structure.

Implemented platform functions to retrieve the soc-id information
f

feat(morello): implement methods to retrieve soc-id information

Added silicon revision in the platform information SDS structure.

Implemented platform functions to retrieve the soc-id information
for the morello SoC platform. SoC revision, which is same as
silicon revision, is fetched from the morello_plat_info structure
and SoC version is populated with the part number from SSC_VERSION
register, and is reflected in bits[0:15] of soc-id.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I8e0c5b2bc21e393e6d638858cc2ea9f4638f04b9

show more ...

fix(versal_net): fix irq for IPI0

Currently isr is not called when IPI0 interrupt occurs.
fix irq number and enable GIC interrupt properly to invoke
registered isr on IPI0 interrupt.

Signed-off-by:

fix(versal_net): fix irq for IPI0

Currently isr is not called when IPI0 interrupt occurs.
fix irq number and enable GIC interrupt properly to invoke
registered isr on IPI0 interrupt.

Signed-off-by: Trung Tran <trung.tran@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id0408b3a560b25234886a9fa01c4ed248d1d1532

show more ...

Merge "fix(tegra): append major revision to the chip_id value" into integration

Merge "fix(ti): do not take system power reference in bl31_platform_setup()" into integration

Merge "style: remove useless trailing semicolon and line continuations" into integration

feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c7111

feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f

show more ...

feat(qemu): make coherent memory section optional

Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent
memory section is not required for them and should be an optional
section.

S

feat(qemu): make coherent memory section optional

Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent
memory section is not required for them and should be an optional
section.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I03c8e9148ca1780b8af92024359698f4452f7129

show more ...

refactor(qemu): make use of setup_page_tables()

Use the setup_page_tables() helper function to setup page tables.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I0bca4e463ed68abf2e

refactor(qemu): make use of setup_page_tables()

Use the setup_page_tables() helper function to setup page tables.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I0bca4e463ed68abf2ef1c79fc8e5cb2b635fcd1c

show more ...

Merge "fix(tegra210): support legacy SMC_ID 0xC2FEFE00" into integration

Merge changes from topic "xlnx_ipi_fix" into integration

* changes:
fix(xilinx): handle CRC failure in IPI callback
fix(xilinx): handle CRC failure in IPI

fix(tegra210): support legacy SMC_ID 0xC2FEFE00

This patch introduces a workaround to support the legacy SMC FID
0xC2FEFE00 to maintain compatibility with older software components.

Change-Id: Icf2

fix(tegra210): support legacy SMC_ID 0xC2FEFE00

This patch introduces a workaround to support the legacy SMC FID
0xC2FEFE00 to maintain compatibility with older software components.

Change-Id: Icf2ef9cfa6b28c09bbab325a642d0b3b20b23535
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

show more ...

fix(tegra): append major revision to the chip_id value

This patch appends the chip's major revision to the chip id value
to form the SoC version value expected by the SMCCC_GET_SOC_VERSION
function

fix(tegra): append major revision to the chip_id value

This patch appends the chip's major revision to the chip id value
to form the SoC version value expected by the SMCCC_GET_SOC_VERSION
function ID.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I09118f446f6b8198588826d4a161bd97dcb6a581

show more ...

Merge changes from topic "imx8m_misc_changes" into integration

* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(im

Merge changes from topic "imx8m_misc_changes" into integration

* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(imx8mq): correct the slot ack setting for STOP mode
feat(imx8mq): add anamix pll override setting for DSM mode
feat(imx8mq): add workaround code for ERR11171 on imx8mq
feat(imx8mq): add the dram retention support for imx8mq
feat(imx8mq): add version for B2
fix(imx8m): backup mr12/14 value from lpddr4 chip
fix(imx8m): add ddr4 dvfs sw workaround for ERR050712
fix(imx8m): fix coverity out of bound access issue
fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0
feat(imx8m): add more dram pll setting
fix(imx8m): fix the current fsp init
fix(imx8m): fix the rank to rank space issue
fix(imx8m): fix the dfiphymaster setting after dvfs
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
fix(imx8m): correct the rank info get fro mstr
feat(imx8m): fix the ddr4 dvfs random hang on imx8m

show more ...

style: remove useless trailing semicolon and line continuations

found using checkpatch.pl[1]

[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl

S

style: remove useless trailing semicolon and line continuations

found using checkpatch.pl[1]

[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7957c9694300fefb85d11f7819c43af95271f14c

show more ...

fix(xilinx): handle CRC failure in IPI callback

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read_callb() logs error message but don't return
error code to upper layers.

fix(xilinx): handle CRC failure in IPI callback

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read_callb() logs error message but don't return
error code to upper layers.

Added CRC failure specific error code which will be returned by
pm_ipi_buff_read_callb() if CRC validation fails.

Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: I2eaca073e2bf325a8c86b1820bdd7cca487b783e

show more ...