chore(zynqmp): print entry address to Secure and NS world

The base address for BL32 and BL33 is read from the FSBL to TF-A
handoff params.
Print the base address for BL32 and BL33 as entry to the se

chore(zynqmp): print entry address to Secure and NS world

The base address for BL32 and BL33 is read from the FSBL to TF-A
handoff params.
Print the base address for BL32 and BL33 as entry to the secure and
non-secure world respectively in the release build.

Change-Id: Icc976fccb56b565f78001d87b02180ced6437a43
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "feat_state_part4" into integration

* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
ref

Merge changes from topic "feat_state_part4" into integration

* changes:
refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SEL2 to new feature handling
refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED
refactor(cpufeat): align FEAT_SB to new feature handling
refactor(cpufeat): use alternative encoding for "SB" barrier
refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED
fix(cpufeat): make stub enable functions "static inline"
fix(mpam): feat_detect: support major/minor

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Merge "fix(fvp): unconditionally include lib/psa headers" into integration

Merge "fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4" into integration

Merge "fix(versal-net): use spin_lock instead of bakery_lock" into integration

fix(fvp): unconditionally include lib/psa headers

Included lib/psa headers uncondiitionally to leverage their
use across different FVP build configurations.

Change-Id: I3417925e544d9ec20606a2ffba3d

fix(fvp): unconditionally include lib/psa headers

Included lib/psa headers uncondiitionally to leverage their
use across different FVP build configurations.

Change-Id: I3417925e544d9ec20606a2ffba3d46ef7adaa730
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(sc7280): add support for PSCI_OS_INIT_MODE

Enable PSCI_OS_INIT_MODE support for sc7280.

Change-Id: If94d59190c0bd876e748cd80b2641ce7616fd817
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>

feat(fvp): enable support for PSCI OS-initiated mode

Change-Id: I4cd6d2bd7ec7f581bd525d5323a3b54e855e2e51
Signed-off-by: Wing Li <wingers@google.com>

fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4

The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions

fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4

The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions
are received simultaneously from different sources. This hardware issue
impacts NVIDIA server platforms that use more than two T241 chips
interconnected. Each chip has support for 320 {E}SPIs.

This issue occurs when multiple packets from different GICs are
incorrectly interleaved at the target chip. The erratum text below
specifies exactly what can cause multiple transfer packets susceptible
to interleaving and GIC state corruption. GIC state corruption can
lead to a range of problems, including kernel panics, and unexpected
behavior.

Erratum documentation:
https://developer.nvidia.com/docs/t241-fabric-4/nvidia-t241-fabric-4-errata.pdf

The workaround is to ensure that MMIO accesses target the GIC on the
socket that holds the data, for example SPI ranges owned by the socket’s
GIC. This ensures that the GIC will not utilize the inter-socket AXI
Stream interface for servicing these GIC MMIO accesses.

This patch updates the functions that use the GICD_In{E} registers to
ensure that the accesses are directed to the chip that owns the SPI,
instead of using the global alias.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I04e33ba64eb306bd5fdabb56e63cbe273d8cd632

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Merge "fix(fpga): include missing header file" into integration

Merge "fix(versal-net): correct aff level for cpu off" into integration

Merge "fix(build): partially fix qemu aarch32 build" into integration

fix(rcar): add mandatory fields in 'reserved-memory' node

On the R-Car Gen3 boards, u-boot will apply this reserved-memory node
directly on the Linux device-tree.

The linux kernel requires that the

fix(rcar): add mandatory fields in 'reserved-memory' node

On the R-Car Gen3 boards, u-boot will apply this reserved-memory node
directly on the Linux device-tree.

The linux kernel requires that the ranges, #address-cells
and #size-cells values must be set in the reserved-memory node.

Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Change-Id: Ic9b9bd3f2177a224d0931f6a4f4818a87904a493

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fix(fpga): include missing header file

Since transitioning over FEAT_SPE to the new feature checking scheme, we
make use of the new is_feat_spe_supported() function in the Arm FPGA
platform code. Ho

fix(fpga): include missing header file

Since transitioning over FEAT_SPE to the new feature checking scheme, we
make use of the new is_feat_spe_supported() function in the Arm FPGA
platform code. However this missed to include the header file, so the
build broke.

Add the arch_features.h header to make arm_fpga compile again.

Change-Id: I5c8feecfcc6fb5845a6671842850df1943086a58
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(versal-net): use spin_lock instead of bakery_lock

In ARM v8.2 the cache will turn off automatically when cpu power down.
Therefore use the spin_lock instead of bakery_lock for the platform in
wh

fix(versal-net): use spin_lock instead of bakery_lock

In ARM v8.2 the cache will turn off automatically when cpu power down.
Therefore use the spin_lock instead of bakery_lock for the platform in
which HW_ASSISTED_COHERENCY is enabled.

In Versal NET platform HW_ASSISTED_COHERENCY is enabled so it will use
spin lock. In ZynqMP and Versal HW_ASSISTED_COHERENCY is not enabled so
it will use bakery_lock.

Also remove bakery_lock_init() because it is empty.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I18ff939b51f16d7d3484d8564d6ee6c586f363d8

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fix(versal-net): correct aff level for cpu off

CPU suspend is calling validate_power_state PSCI opps which returns
power domain state for CPU suspend according to PSTATE type. In case of
power down

fix(versal-net): correct aff level for cpu off

CPU suspend is calling validate_power_state PSCI opps which returns
power domain state for CPU suspend according to PSTATE type. In case of
power down it assigns PLAT_MAX_OFF_STATE to all affinity level which is
incorrect since for CPU suspend we need to set only MPIDR_AFFLVL0 which
is CPU state. So correct affinity level for CPU suspend.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I39f92790ea74e4cab8e87342e73e1ac211a46fcd

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fix(build): partially fix qemu aarch32 build

While aarch32 isn't currently supported on qemu, platform.mk contains
hard-coded references to aarch64 in BL1_SOURCES which should be ${ARCH}.

This impr

fix(build): partially fix qemu aarch32 build

While aarch32 isn't currently supported on qemu, platform.mk contains
hard-coded references to aarch64 in BL1_SOURCES which should be ${ARCH}.

This improves the situation, but since aarch32/qemu_max.S doesn't exist
and there are other missing files for aarch32, this is only a partial
fix.

Signed-off-by: Rebecca Cran <rebecca@quicinc.com>
Change-Id: I3fa01483e572abfd781ceaecff16ecf57cda8316

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refactor(fvp): use RSS API to retrieve attestation token and key

Retrieved the platform attestation token and delegated realm attestation
key through the PSA delegated attestation layer.

Even thoug

refactor(fvp): use RSS API to retrieve attestation token and key

Retrieved the platform attestation token and delegated realm attestation
key through the PSA delegated attestation layer.

Even though FVP doesn't support RSS hardware today, it can still
leverage the RSS implementation of these PSA interfaces in their mocking
form (see PLAT_RSS_NOT_SUPPORTED).

Therefore, platform APIs now call these PSA interfaces instead of
directly providing these hardcoded values.

Change-Id: I31d0ca58f6f1a444f513d954da4e3e67757321ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED

At the moment we only support for FEAT_RNG to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime

refactor(cpufeat): enable FEAT_RNG for FEAT_STATE_CHECKED

At the moment we only support for FEAT_RNG to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (FEAT_RNG=2), by splitting
is_armv8_5_rng_present() into an ID register reading function and a second
function to report the support status. That function considers both build
time settings and runtime information (if needed), and is used before we
access the RNDRRS system register.

Change the QEMU platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I1a4a538d5ad395fead7324f297d0056bda4f84cb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): align FEAT_SEL2 to new feature handling

In ARMv8.4, the EL2 exception level got added to the secure world.
Adapt and rename the existing is_armv8_4_sel2_present() function, to
ali

refactor(cpufeat): align FEAT_SEL2 to new feature handling

In ARMv8.4, the EL2 exception level got added to the secure world.
Adapt and rename the existing is_armv8_4_sel2_present() function, to
align its handling with the other CPU features.

Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED

At the moment we only support for FEAT_NV2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime

refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED

At the moment we only support for FEAT_NV2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (CTX_INCLUDE_NEVE_REGS=2), by
splitting get_armv8_4_feat_nv_support() into an ID register reading
function and a second function to report the support status. That
function considers both build time settings and runtime information
(if needed), and is used before we access the VNCR_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_nv2_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I85b080641995fb72cfd4ac933f7a3f75770c2cb9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED

At the moment we only support FEAT_TWED to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime d

refactor(cpufeat): enable FEAT_TWED for FEAT_STATE_CHECKED

At the moment we only support FEAT_TWED to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_FEAT_TWED=2), by splitting
is_armv8_6_twed_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we set the trap delay time.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I58626230ef0af49886c0a197abace01e81f661d2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED

At the moment we only support FEAT_CSV2_2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runti

refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED

At the moment we only support FEAT_CSV2_2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_FEAT_CSV2_2=2), by splitting
is_armv8_0_feat_csv2_2_present() into an ID register reading function
and a second function to report the support status. That function
considers both build time settings and runtime information (if needed),
and is used before we access the SCXTNUM_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_csv2_2_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I89c7bc883e6a65727fdbdd36eb3bfbffb2196da7
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED

At the moment we only support FEAT_ECV to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime det

refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED

At the moment we only support FEAT_ECV to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_FEAT_ECV=2), by splitting
is_feat_ecv_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access the CNTPOFF_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_ecv_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I4acd5384929f1902b62a87ae073aafa1472cd66b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED

At the moment we only support FEAT_PAN to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime det

refactor(cpufeat): enable FEAT_PAN for FEAT_STATE_CHECKED

At the moment we only support FEAT_PAN to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_FEAT_PAN=2), by splitting
is_armv8_1_pan_present() into an ID register reading function and a
second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we PAN specific setup.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I58e5fe8d3c9332820391c7d93a8fb9dba4cf754a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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