feat(qemu-sbsa): support s-el2 and s-el1 spmc

Reserve memory for TB_FW_CONFIG and TOS_FW_CONFIG if configured with
SPD=spmd and optionally SPMD_SPM_AT_SEL2=1.

Change-Id: I2f27502b6d5f9f0131ab8ba273

feat(qemu-sbsa): support s-el2 and s-el1 spmc

Reserve memory for TB_FW_CONFIG and TOS_FW_CONFIG if configured with
SPD=spmd and optionally SPMD_SPM_AT_SEL2=1.

Change-Id: I2f27502b6d5f9f0131ab8ba273ab738de5643d45
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Merge changes Ibc52a4fc,Ieb56af33 into integration

* changes:
build(allwinner): disable unneeded CVE workarounds and MPAM
fix(cpus): use correct Makefile indentation for CVE-2018-3639 check

feat(ti): am62lx init: boot notif and version msg

Consume the boot notification on this platform before we start further
communication with the system-firmware.

Change-Id: Ia9e5d8d616d7d9cd50ee5de2

feat(ti): am62lx init: boot notif and version msg

Consume the boot notification on this platform before we start further
communication with the system-firmware.

Change-Id: Ia9e5d8d616d7d9cd50ee5de2e4c8abe06104dc05
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(ti): add mmu regions for am62l soc

Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware b

feat(ti): add mmu regions for am62l soc

Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware blocks are accessible to the A53 cores on the
AM62L SoC.
Use 4K aligned address sizes wherever applicable, and update the
file header comment from "K3 SOC specific bl31_setup" to "k3low SoC
specific bl31_setup" to accurately represent the platform specific
nature of this file.
As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE
to WKUP_CTRL_MMR0_BASE to make name shorter.

Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(ti): build generic timer

Also, make sure we init the generic timer as part of the soc init
on am62lx as we use it later for delays

Change-Id: I921f4e4120ddaba588eb5b876231435fff3f7f3c
Signed-o

feat(ti): build generic timer

Also, make sure we init the generic timer as part of the soc init
on am62lx as we use it later for delays

Change-Id: I921f4e4120ddaba588eb5b876231435fff3f7f3c
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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Merge changes I32c5be5d,I15a652a0 into integration

* changes:
fix(qemu): add reason parameter to MEC update
refactor(rmmd): modify MEC update call to meet FIRME

fix(spm): change the SMMUv3TestEngine being used

Use a test engine that's not connected via PCIe as those can't make
Secure accesses.

Change-Id: I6f7f235d022090189782381bc88e67de64c11927
Signed-off

fix(spm): change the SMMUv3TestEngine being used

Use a test engine that's not connected via PCIe as those can't make
Secure accesses.

Change-Id: I6f7f235d022090189782381bc88e67de64c11927
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(qemu): add reason parameter to MEC update

The FIRME MFI_MEC_REFRESH call takes a reason parameter. Add it to the
QEMU callback for compatibility.

Change-Id: I32c5be5dbce44102650f9312c44e1d00a31

fix(qemu): add reason parameter to MEC update

The FIRME MFI_MEC_REFRESH call takes a reason parameter. Add it to the
QEMU callback for compatibility.

Change-Id: I32c5be5dbce44102650f9312c44e1d00a3146eb9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[

refactor(rmmd): modify MEC update call to meet FIRME

Previous version of MEC refresh call was not compliant with FIRME [1].
This patch modifies the call so it is compliant with the specification.

[1] https://developer.arm.com/documentation/den0149/1-0alp0/

Change-Id: I15a652a021561edca16e79d127e6f08975cf1361
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge "fix(rcar4): drop unused plat_pm_scmi" into integration

build(allwinner): disable unneeded CVE workarounds and MPAM

There are a number of workarounds for CVEs related to sidechannel
attacks on some CPU cores, most of them listed here:
https://developer.a

build(allwinner): disable unneeded CVE workarounds and MPAM

There are a number of workarounds for CVEs related to sidechannel
attacks on some CPU cores, most of them listed here:
https://developer.arm.com/documentation/110280/latest/
Also there are two other CVEs:
https://developer.arm.com/documentation/110324/latest/
https://developer.arm.com/documentation/110326/latest/

As these page reveals, those workaround do not apply to the Cortex-A53
(or A55) cores, so we can safely disable them in the Allwinner build
recipes, since they only use those two cores so far.

Also disable FEAT_MPAM, which is one of the only three later features
that are enabled default, but are not enabled in Cortex-A53 or A55
cores. Use the opportunity to group those options together and improve
the comment.

This decreases the code size by a few hundred bytes.

Change-Id: Ibc52a4fc9b8f5d9b2b28a2ce13d3ab99b63e9640
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "feat(versal2): remove handoff entry from tl" into integration

fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+re

fix(rcar4): drop unused plat_pm_scmi

Drop unused plat_pm_scmi.c and related platform.mk entries.
If this is ever going to be used, this can be reinstated.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Icdb5188cba97be5dfccb240f773288a54662e977

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fix: replace stray BL2_AT_EL3 with RESET_TO_BL2

For FVP, patch 259b67c08 should have used the latter but introduced the
former. That was a mistake, correct it.

The nuvoton platform seems to have co

fix: replace stray BL2_AT_EL3 with RESET_TO_BL2

For FVP, patch 259b67c08 should have used the latter but introduced the
former. That was a mistake, correct it.

The nuvoton platform seems to have copied arm_def.h and would have been
missed at some point. Update that too.

Change-Id: I28123186bb4b69c5d5154dcdd24e5dee9d9e33b8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm

fvp_stmm_l2_sp_list.dts is used to load StandaloneMm with rust-spmc.

This sp information will be included into fvp_tb_fw_config.dts
by

feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm

fvp_stmm_l2_sp_list.dts is used to load StandaloneMm with rust-spmc.

This sp information will be included into fvp_tb_fw_config.dts
by specifying ARM_BL2_SP_LIST_DTS build option with this file.

Change-Id: I42b1ed9a04ac29b1a3c31f7267b337d4e3036c10
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry

For compatibility with SPMCs that obtain
event log information from DT_SPMC_MANIFEST,
ensure the event log is updated when TF-A

feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry

For compatibility with SPMCs that obtain
event log information from DT_SPMC_MANIFEST,
ensure the event log is updated when TF-A uses firmware handoff.

Change-Id: Iafc11c63c86c2ee67481e3085d2e8390d5f99cea
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition

PLAT_ARM_SPMC_SP_MANIFEST_SIZE is used to allocate transfer entry
when TF-A is built with TRANSFER_LIST to pass:
- StandaloneMm manifest w

feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition

PLAT_ARM_SPMC_SP_MANIFEST_SIZE is used to allocate transfer entry
when TF-A is built with TRANSFER_LIST to pass:
- StandaloneMm manifest with TL_TAG_DT_FFA_MANIFEST tag
in case of SPMC_AT_EL3

- SPMC manifest (i.e) rust-spmc.

Therefore, move the PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
under the TRNASFER_LIST & SPD_spmd condition and increase
the size of TRANSFER_LIST as much as PLAT_ARM_SPMC_SP_MANIFEST_SIZE

Change-Id: If5e4c184fcf3aa683554f6d49caf78a5f6bfc2d1
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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Merge "fix(xilinx): typecast operands to match data type" into integration

feat(spmd): get spmc manifest from xferlist

When TRANSFER_LIST build option is used, arg0 doesn't pass the
SPMC manifest. but it should be passed to load SPMC.

For this, adds the spmc manifest entr

feat(spmd): get spmc manifest from xferlist

When TRANSFER_LIST build option is used, arg0 doesn't pass the
SPMC manifest. but it should be passed to load SPMC.

For this, adds the spmc manifest entry in the transfer list
with TL_TAG_DT_SPMC_MANIFEST tag and
let spmd load the spmc manifest from transfer list.

Change-Id: I3b84c3d8a17bba4ac94afe00e1e19044449360b0
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU p

feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU power driver, Gen4 (H)SCIF driver, and function to get canary for
stack protector. Unlike Gen3, the Gen4 uses only TFA BL31 during boot.

Change-Id: Ic0eb8638a85757f997f29fc524c118c3e5d5135a
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Jing Dan <jing.dan.nx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Masashi Ozaki <masashi.ozaki.te@renesas.com>
Signed-off-by: Taichiro Yokoyama <taichiro.yokoyama.ns@hitachi.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Tsukasa Kawaguchi <tsukasa.kawaguchi.aw@hitachi.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Vincent Bryce <vincent.bryce@cogentembedded.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
---
NOTE: This patch is squashed and cleaned up from large stack of patches
from multiple authors. SoB line from each author is included here,
the author of this commit is set to myself although that is most
certainly not accurate.

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Merge changes from topic "rmm-lfa" into integration

* changes:
feat(rmmd): add RMM_RESERVE_MEMORY SMC handler
feat(rmmd): add per-CPU activation token

feat(versal): add support to clear PM specific data

During a kexec restart, only the kernel is reloaded while TF-A state
remains unchanged, causing a mismatch between kernel and TF-A states.
To reso

feat(versal): add support to clear PM specific data

During a kexec restart, only the kernel is reloaded while TF-A state
remains unchanged, causing a mismatch between kernel and TF-A states.
To resolve this, add support for the TF_A_CLEAR_PM_STATE API, which
clears TF-A PM state.

Change-Id: I6b460f8cd4293381d3a9c574dd144521b8e54f8a
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal-net): fix coverity violation prevent buffer overrun

Coverity reported potential memory corruption issues in
bl31_early_platform_setup2() (CIDs 487973 and 487972):

- CID 487973 (ARRAY_VS_

fix(versal-net): fix coverity violation prevent buffer overrun

Coverity reported potential memory corruption issues in
bl31_early_platform_setup2() (CIDs 487973 and 487972):

- CID 487973 (ARRAY_VS_SINGLETON): "&boot_mode" was passed to
get_boot_mode(), which treats the argument as an array. This could
lead to misinterpretation of adjacent memory.
- CID 487972 (OVERRUN): Passing "&boot_mode" (a single 4-byte element)
allowed get_boot_mode() to access out-of-bounds indices, resulting in
a possible buffer overrun.

Changed boot_mode from a single variable to an array sized according
to the return payload, preventing singleton pointer violation.

Change-Id: I53944db10b694d1599da0e5b1fbd30a97e83803c
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I5fcf6578,Ic7792603 into integration

* changes:
fix(xilinx): fix missing security flag in suspend path
feat(zynqmp): mark IPI calls secure/non-secure