feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD

Upower will check the LPAV ownership when power off the SRAM or PS.
if the LPAV owner is not APD, then the power off will return failure.

feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD

Upower will check the LPAV ownership when power off the SRAM or PS.
if the LPAV owner is not APD, then the power off will return failure.
Add similar checking in SCMI PD driver to skip the power off to avoid
failure print causing suspend/resume not work.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I9dc657c2277129ac90a792232f734c08fca5f997

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feat(imx8ulp): add system power off support

On i.MX8ULP, we need to use the APD deep power down(DPD) mode
to support the system power off function. when APD enter
power off mode, only the RTD can re

feat(imx8ulp): add system power off support

On i.MX8ULP, we need to use the APD deep power down(DPD) mode
to support the system power off function. when APD enter
power off mode, only the RTD can re-kick it and boot from ROM.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifb42db0a7cf87b932160c59b47eca4d0f08f8cdf

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feat(imx8ulp): add APD power down mode(PD) support in system suspend

The APD can be put into PD mode when linux suspend(mem). This patch
add the support for it. As the whole AP domain's context will

feat(imx8ulp): add APD power down mode(PD) support in system suspend

The APD can be put into PD mode when linux suspend(mem). This patch
add the support for it. As the whole AP domain's context will be lost,
so we must save the necessary HW module states before entering PD mode,
and we need to restore those contexts when system wake up. Fot details
about which HW module's state will be lost, please refer to the RM.

When APD enter PD mode, only the wakeup event connected to the WUU
can wakeup APD successfully. The upower wakeup source is used to
wakeup APD by RTD due to the factor that the MU between A core & M
core is not connected into WUU to generate wakeup event.

as the SRAM0 will be power down when APD enters PD mode, so we
need to re-init the scmi channels(resides in the SRAM0). otherwise
the SCMI can NOT work anymore.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I44b0cdc8397e5d6a82081ea6746542e9fa4b9fc1

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feat(imx8ulp): add the basic support for idle & system suspned

Add basic support for the cpuidle(cluster retention) and system
suspend support using the HW sleep mode.

When system enter low power m

feat(imx8ulp): add the basic support for idle & system suspned

Add basic support for the cpuidle(cluster retention) and system
suspend support using the HW sleep mode.

When system enter low power mode after doing reboot twice, APD
will be failed to exit from low power mode successfully. it is
because that after secondary reboot, upower will modify the default
power switch config, then DDR will be off wrongly. So config the
low power mode info explicitly before APD entering any low power
mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ib68bfdfd4b925541e343aef4a5296a542451f86b

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feat(imx8ulp): enable 512KB cache after resume on imx8ulp

The L2 cache size config will be reset to default 256KB,
So we need to switch to 512KB after resume to make sure
the L2 cache size is same a

feat(imx8ulp): enable 512KB cache after resume on imx8ulp

The L2 cache size config will be reset to default 256KB,
So we need to switch to 512KB after resume to make sure
the L2 cache size is same as before suspend.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifd9b3e01829fbd7b1ae4ba00611359330f1a4f83

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feat(imx8ulp): add the initial XRDC support

Add the initial xRDC support on i.MX8ULP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.

feat(imx8ulp): add the initial XRDC support

Add the initial xRDC support on i.MX8ULP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I93ea8e2cebb049e6f20e71cfe50c7583a3228f38

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feat(imx8ulp): allocated caam did for the non secure world

JR1, JR2 and JR3 are available for use by the non secure
world. Setup the A35 core DID for these job rings.

Signed-off-by: Varun Sethi <v.

feat(imx8ulp): allocated caam did for the non secure world

JR1, JR2 and JR3 are available for use by the non secure
world. Setup the A35 core DID for these job rings.

Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If64d4ce11ebff49a2405d8b561b344fcd7b2614f

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feat(imx8ulp): add i.MX8ULP basic support

Add the basic support for i.MX8ULP.

The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an

feat(imx8ulp): add i.MX8ULP basic support

Add the basic support for i.MX8ULP.

The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an Arm Cortex-M33. This combined architecture enables the
device to run a rich operating system (such as Linux) on
the Cortex-A35 core and an RTOS (such as FreeRTOS) on the
Cortex-M33 core. It also includes a Cadence Tensilica Fusion
DSP for low-power audio and a HiFi4 DSP for advanced audio
and machine learning applications.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36

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refactor(tc): reorder config variable defines

They are very scattered, hard to read, and especially hard to track
down. As a result some are duplicate and some are overridden in the
downstream as it

refactor(tc): reorder config variable defines

They are very scattered, hard to read, and especially hard to track
down. As a result some are duplicate and some are overridden in the
downstream as it's simpler.

Put all variables at the top of the platform makefile. Also drop setting
variables that don't change from their default values
(CTX_INCLUDE_EL2_REGS, ARCH, ENABLE_FEAT_RAS, SDEI_SUPPORT,
EL3_EXCEPTION_HANDLING, HANDLE_EA_EL3_FIRST_NS, ENABLE_SPE_FOR_NS).

While we're at it, add some variables that are necessary. SPMD
requires MTE registers to be saved, BRANCH_PROTECTION, as well as
running at SEL2. All of our CPUs are Armv8.7 compliant so we can have
ARM_ARCH_MINOR=7 (and drop ENABLE_TRF_FOR_NS which it includes).

Finally, drop the override directives as there's no reason to prohibit
experimentation (even if incorrect).

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I6ac596934952aab8abf5d4db5220e13a4941a10c

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refactor(tc): correlate secure world addresses with platform_def

Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manife

refactor(tc): correlate secure world addresses with platform_def

Similarly to the memory node in the NS device tree, platform_def already
defines all the necessary values to populate the spmc manifest and NS
related entries automatically. Use the macros directly so any changes
can propagate automatically.

The result of this is that TC3 and above get correct secure world
manifests automatically. They were previously broken.

One "breaking" change is that the FWU region moves. This should have
happened previously but it was missed when the secure portion of DRAM
was increased, leaving it in secure memory. This was caught when going
over the definitions and correlating them should prevent this in the
future.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1415e402be8c70f5e22f28eabddcb53298c57a11

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refactor(tc): move DTB to start of DRAM

Now that tf-a passes the DTB address to BL33, its location doesn't
matter. Since we declare a fixed size for it (32K) put it at the start
of ram to not fragme

refactor(tc): move DTB to start of DRAM

Now that tf-a passes the DTB address to BL33, its location doesn't
matter. Since we declare a fixed size for it (32K) put it at the start
of ram to not fragment memory. This has the added benefit of
"supporting" larger kernel sizes which are breaking with the current
location.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib0e4e5cf780bd58a49a34d72085b0a0914c340ed

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feat(tc): add memory node in the device tree

With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't com

feat(tc): add memory node in the device tree

With new TC revisions, memory banks move around which requires an update
in platform_def. It also requires an update in the device tree which
doesn't come naturally. To avoid this, add the memory node such that it
uses the macros defined in platform_def.

By doing this we can put u-boot out of its misery in trying to come up
with the correct memory node and tf-a's device tree becomes complete.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia92cc6931abb12be2856ac3fb1455e4f3005b326

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feat(tc): pass the DTB address to BL33 in R0

The DTB that tf-a loads is already used in BL33 directly with the
address hardcoded. As this address is prone to changing, pass it forward
so we can avoi

feat(tc): pass the DTB address to BL33 in R0

The DTB that tf-a loads is already used in BL33 directly with the
address hardcoded. As this address is prone to changing, pass it forward
so we can avoid breakage in the future.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I7a42f72ecc00814b9f0a4bf5605d70cb53ce2ff4

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feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU

feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU correctly
for DPU and GPU.

These will allow easier experimentation in the future without
ad-hoc changes needed in the dts file for any sort of analysis
that requires testing different paths.

For TC3 however, the DPU is in an always on power domain so SCMI power
domains are not supported.

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1

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feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The dif

feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The differences are:
* addresses of GIC and UART
* displays (FPGA uses 4k)
* ethernet devices and SD card (it's non removable on the FPGA)

Their frequencies are also different. The FVP simulates certain
frequencies but isn't very sensitive when we disregard them. To keep
code similar, update them with the FPGA values. This keeps working on
FVP even if slightly incorrect.

Also add an option for the DPU to either use fixed clocks or SCMI set
clocks, hidden behind a flag. This is useful during bringup and because
SCMI may not necessarily work on FPGA.

Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Co-developed-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Co-developed-by: Usama Arif <usama.arif@arm.com>
Co-developed-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic7a4bfc302673a3a6571757e23a9e6184fba2a13

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feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arran

feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arrangement).

Introduce these differences and gate them behind a new TARGET_FLAVOUR
flag which defaults to FVP for compatibility.

While updating CPUs, it's a good time to do TC3 too. It has different
cores in a different configuration again, so it needs different capacity
values. Those have been derived using GeekBench 6.0 ST on the FPGA.

Finally GPU and DPU power domains are 1 above the CPUs so make that
relative.

In the end, the big/mid/little configurations are:
* TC2 FVP: 1/3/4
* TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core)
* TC3 both: 2/4/2 (with new capacities)

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b

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feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utili

feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utility space address (needed for MPAM) is different
* no CMN (and therefore cmn-pmu)
* the uart clock is different

This requires the dts to be different between revisions for the first
time. Introduce a tc_vers.dtsi that includes only definitions for things
that are different.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2940d87a69ea93502b7f5a22a539e4b70a63e827

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feat(tc): allow booting from DRAM

In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRA

feat(tc): allow booting from DRAM

In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRAM1 bank. If we want to access it it needs
to be mapped to memory.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I45e0fbb016e8f615d41b6ad9da0d1e7b466ece72

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Merge "build(corstone1000): add CORSTONE1000_WITH_BL32 preprocessor flag" into integration

build(fpga): correctly handle gcc as linker for LTO

When LTO is enabled and gcc is used as a linker, then option for a
linker have to be provided with a -Wl prefix to gcc.

To build PLAT=arm_fpga wi

build(fpga): correctly handle gcc as linker for LTO

When LTO is enabled and gcc is used as a linker, then option for a
linker have to be provided with a -Wl prefix to gcc.

To build PLAT=arm_fpga with LTO enabled extra '-nostdlib' has to be
supplied to the linker at least, otherwise build fails with an error
about many undefined references in libc.
Since this option is defined as part of common TF_LDFLAGS already,
just use that variable with couple extra options.

Change-Id: Iaab72d894317c91af5b7d770652e4353b32aae88
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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fix(rockchip): add support for building with LTO enabled

Using the asm .incbin statement in C sources breaks gcc wrapper.
Build fails with a following errors:
/tmp/ccRXHTU4.s: Assembler messages:

fix(rockchip): add support for building with LTO enabled

Using the asm .incbin statement in C sources breaks gcc wrapper.
Build fails with a following errors:
/tmp/ccRXHTU4.s: Assembler messages:
/tmp/ccRXHTU4.s:34: Warning: dwarf line number information for .pmusram.incbin ignored
...
/tmp/ccRXHTU4.s:2119: Warning: dwarf line number information for .pmusram.incbin ignored
/tmp/ccRXHTU4.s:112497: Error: leb128 operand is an undefined symbol: .LVU5
/tmp/ccRXHTU4.s:112498: Error: leb128 operand is an undefined symbol: .LVU6
/tmp/ccRXHTU4.s:112507: Error: leb128 operand is an undefined symbol: .LVU9
...
/tmp/ccRXHTU4.s:115407: Error: leb128 operand is an undefined symbol: .LVU668
/tmp/ccRXHTU4.s:115408: Error: leb128 operand is an undefined symbol: .LVU710
/tmp/ccRXHTU4.s:115409: Error: leb128 operand is an undefined symbol: .LVU713
lto-wrapper: fatal error: aarch64-none-elf-gcc returned 1 exit status
compilation terminated.
aarch64-none-elf/bin/ld: error: lto-wrapper failed
collect2: error: ld returned 1 exit status

Fix it in a similar way to what the Linux kernel does, see commit
919aa45e43a84d40c27c83f6117cfa6542cee14e (MODSIGN: Avoid using .incbin
in C source). [1]

1. https://lkml.org/lkml/2012/12/4/136

Change-Id: Iecc19729ce59e8c3b3c30fa37b1fddef95e83c96
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total c

feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total compute platform. To make it fit with Op-tee we need to reduce
its available memory.

Also, reserve 4 MB for stmm communication used for firmware update.
The firmware update secure partition and u-boot communicates using the
stmm communication layer and it needs a dedicated memory region.

Co-developed-by: Sergio Alves <sergio.dasilvalves@arm.com>
Co-developed-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Tudor Cretu <tudor.cretu@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0427549845f6c7650b8ef4e450d387fe9702a847

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feat(tc): add spmc manifest with trusty sp

Add SPMC manifest with Trusty SP. Define Trusty's load address,
vcpu count, memory size.

Co-developed-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Co

feat(tc): add spmc manifest with trusty sp

Add SPMC manifest with Trusty SP. Define Trusty's load address,
vcpu count, memory size.

Co-developed-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Co-developed-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1f7d7c1c6a5ef67541097ab04670343282458aeb

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refactor(tc): unify all the spmc manifests

The manifests describe the same hardware layout with only the secure
partitions being different. Factor it out so it can be shared and only
add the VM info

refactor(tc): unify all the spmc manifests

The manifests describe the same hardware layout with only the secure
partitions being different. Factor it out so it can be shared and only
add the VM information separately.

This has some deliberate side effects: the test configuration gets the
full secure memory address space and drops the 0x7000000 region as that
was accidentally copied over from the FVP platform and doesn't apply to
TC.

Also optee unconditionally gets the smaller mem_size as it's been
working fine and simplifies the manifest.

Small touch up is that mem_size-s are now in hex but otherwise the same
number.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iea23f9769235eea32afa374952b9a0e4f6d3e9a1

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feat(arm): add trusty_sp_fw_config build option

Also increase add PLAT_ARM_SP_MAX_SIZE to override the default
ARM_SP_MAX_SIZE to support Trusty image and move OPTEE_SP_FW_CONFIG
documentation to bu

feat(arm): add trusty_sp_fw_config build option

Also increase add PLAT_ARM_SP_MAX_SIZE to override the default
ARM_SP_MAX_SIZE to support Trusty image and move OPTEE_SP_FW_CONFIG
documentation to build-internals.rst as it's not externally set-able.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ief90ae9113d32265ee2200f35f3e517b7b9a4bea

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