1 /* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/board/common/board_css_def.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_def.h> 15 #include <plat/arm/common/arm_spm_def.h> 16 #include <plat/arm/css/common/css_def.h> 17 #include <plat/arm/soc/common/soc_css_def.h> 18 #include <plat/common/common_def.h> 19 20 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 21 22 /* 23 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 24 * its base is ARM_AP_TZC_DRAM1_BASE. 25 * 26 * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: 27 * - BL32_BASE when SPD_spmd is enabled 28 * - Region to load secure partitions 29 * 30 * 31 * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE 32 * | | 33 * | SPMC | 34 * | SP | 35 * | (96MB) | 36 * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE 37 * | AP | 38 * | EL3 Monitor | 39 * | SCP | 40 * | (16MB) | 41 * 0xFFFF_FFFF ------------------ 42 * 43 * 44 */ 45 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 46 TC_TZC_DRAM1_SIZE) 47 #define TC_TZC_DRAM1_SIZE 96 * SZ_1M /* 96 MB */ 48 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 49 TC_TZC_DRAM1_SIZE - 1) 50 51 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 52 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 53 ARM_TZC_DRAM1_SIZE - \ 54 TC_TZC_DRAM1_SIZE) 55 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \ 56 TC_NS_DRAM1_SIZE - 1) 57 58 /* 59 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 60 */ 61 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 62 TC_NS_DRAM1_BASE, \ 63 TC_NS_DRAM1_SIZE, \ 64 MT_MEMORY | MT_RW | MT_NS) 65 66 67 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 68 TC_TZC_DRAM1_BASE, \ 69 TC_TZC_DRAM1_SIZE, \ 70 MT_MEMORY | MT_RW | MT_SECURE) 71 72 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x83000000) 73 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 74 75 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 76 PLAT_HW_CONFIG_DTB_BASE, \ 77 PLAT_HW_CONFIG_DTB_SIZE, \ 78 MT_MEMORY | MT_RO | MT_NS) 79 /* 80 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 81 * max size of BL32 image. 82 */ 83 #if defined(SPD_spmd) 84 #define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) 85 86 #define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR 87 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 88 #endif 89 90 /* 91 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 92 * plat_arm_mmap array defined for each BL stage. 93 */ 94 #if defined(IMAGE_BL31) 95 # if SPM_MM 96 # define PLAT_ARM_MMAP_ENTRIES 9 97 # define MAX_XLAT_TABLES 7 98 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 99 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 100 # else 101 # define PLAT_ARM_MMAP_ENTRIES 8 102 # define MAX_XLAT_TABLES 8 103 # endif 104 #elif defined(IMAGE_BL32) 105 # define PLAT_ARM_MMAP_ENTRIES 8 106 # define MAX_XLAT_TABLES 5 107 #elif !USE_ROMLIB 108 # define PLAT_ARM_MMAP_ENTRIES 11 109 # define MAX_XLAT_TABLES 7 110 #else 111 # define PLAT_ARM_MMAP_ENTRIES 12 112 # define MAX_XLAT_TABLES 6 113 #endif 114 115 /* 116 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 117 * plus a little space for growth. 118 */ 119 #define PLAT_ARM_MAX_BL1_RW_SIZE 0x12000 120 121 /* 122 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 123 */ 124 125 #if USE_ROMLIB 126 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 127 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 128 #else 129 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 130 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 131 #endif 132 133 /* 134 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 135 * little space for growth. Current size is considering that TRUSTED_BOARD_BOOT 136 * and MEASURED_BOOT is enabled. 137 */ 138 # define PLAT_ARM_MAX_BL2_SIZE 0x29000 139 140 141 /* 142 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 143 * calculated using the current BL31 PROGBITS debug size plus the sizes of 144 * BL2 and BL1-RW. Current size is considering that TRUSTED_BOARD_BOOT and 145 * MEASURED_BOOT is enabled. 146 */ 147 #define PLAT_ARM_MAX_BL31_SIZE 0x60000 148 149 /* 150 * Size of cacheable stacks 151 */ 152 #if defined(IMAGE_BL1) 153 # if TRUSTED_BOARD_BOOT 154 # define PLATFORM_STACK_SIZE 0x1000 155 # else 156 # define PLATFORM_STACK_SIZE 0x440 157 # endif 158 #elif defined(IMAGE_BL2) 159 # if TRUSTED_BOARD_BOOT 160 # define PLATFORM_STACK_SIZE 0x1000 161 # else 162 # define PLATFORM_STACK_SIZE 0x400 163 # endif 164 #elif defined(IMAGE_BL2U) 165 # define PLATFORM_STACK_SIZE 0x400 166 #elif defined(IMAGE_BL31) 167 # if SPM_MM 168 # define PLATFORM_STACK_SIZE 0x500 169 # else 170 # define PLATFORM_STACK_SIZE 0xa00 171 # endif 172 #elif defined(IMAGE_BL32) 173 # define PLATFORM_STACK_SIZE 0x440 174 #endif 175 176 /* 177 * In the current implementation the RoT Service request that requires the 178 * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 179 * maximum required buffer size is calculated based on the platform-specific 180 * needs of this request. 181 */ 182 #define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x500 183 184 #define TC_DEVICE_BASE 0x21000000 185 #define TC_DEVICE_SIZE 0x5f000000 186 187 // TC_MAP_DEVICE covers different peripherals 188 // available to the platform 189 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 190 TC_DEVICE_BASE, \ 191 TC_DEVICE_SIZE, \ 192 MT_DEVICE | MT_RW | MT_SECURE) 193 194 195 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 196 V2M_FLASH0_SIZE, \ 197 MT_DEVICE | MT_RO | MT_SECURE) 198 199 #define PLAT_ARM_NSTIMER_FRAME_ID 0 200 201 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 202 203 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 204 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 205 206 #define PLAT_ARM_NSRAM_BASE 0x06000000 207 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 208 209 #if TARGET_PLATFORM <= 2 210 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 211 #elif TARGET_PLATFORM == 3 212 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 213 #endif /* TARGET_PLATFORM == 3 */ 214 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 215 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 216 217 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp) 218 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \ 219 INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \ 220 GIC_HIGHEST_SEC_PRIORITY, grp, \ 221 GIC_INTR_CFG_LEVEL) 222 223 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 224 PLAT_SP_IMAGE_NS_BUF_SIZE) 225 226 #define PLAT_ARM_SP_MAX_SIZE U(0x2000000) 227 228 /******************************************************************************* 229 * Memprotect definitions 230 ******************************************************************************/ 231 /* PSCI memory protect definitions: 232 * This variable is stored in a non-secure flash because some ARM reference 233 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 234 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 235 */ 236 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 237 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 238 239 /* Secure Watchdog Constants */ 240 #define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000) 241 #define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000) 242 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 243 #define SBSA_SECURE_WDOG_INTID 86 244 245 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 246 247 /* Index of SDS region used in the communication with SCP */ 248 #define SDS_SCP_AP_REGION_ID U(0) 249 /* Index of SDS region used in the communication with RSS */ 250 #define SDS_RSS_AP_REGION_ID U(1) 251 /* 252 * Memory region for RSS's shared data storage (SDS) 253 * It is placed right after the SCMI payload area. 254 */ 255 #define PLAT_ARM_RSS_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \ 256 CSS_SCMI_PAYLOAD_SIZE_MAX) 257 258 #define PLAT_ARM_CLUSTER_COUNT U(1) 259 #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 260 #define PLAT_MAX_CPUS_PER_CLUSTER U(14) 261 #else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 262 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 263 #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */ 264 #define PLAT_MAX_PE_PER_CPU U(1) 265 266 #define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT) 267 268 /* Message Handling Unit (MHU) base addresses */ 269 #if TARGET_PLATFORM <= 2 270 #define PLAT_CSS_MHU_BASE UL(0x45400000) 271 #elif TARGET_PLATFORM == 3 272 #define PLAT_CSS_MHU_BASE UL(0x46000000) 273 #endif /* TARGET_PLATFORM == 3 */ 274 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 275 276 /* TC2: AP<->RSS MHUs */ 277 #define PLAT_RSS_AP_SND_MHU_BASE UL(0x2A840000) 278 #define PLAT_RSS_AP_RCV_MHU_BASE UL(0x2A850000) 279 280 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 281 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 282 283 /* 284 * Physical and virtual address space limits for MMU in AARCH64 285 */ 286 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 287 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 288 289 /* GIC related constants */ 290 #define PLAT_ARM_GICD_BASE UL(0x30000000) 291 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 292 #define PLAT_ARM_GICR_BASE UL(0x30080000) 293 294 /* 295 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 296 * SCP_BL2 size plus a little space for growth. 297 */ 298 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 299 300 /* 301 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 302 * SCP_BL2U size plus a little space for growth. 303 */ 304 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 305 306 /* TZC Related Constants */ 307 #define PLAT_ARM_TZC_BASE UL(0x25000000) 308 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 309 310 #define TZC400_OFFSET UL(0x1000000) 311 #define TZC400_COUNT 4 312 313 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 314 (n * TZC400_OFFSET)) 315 316 #define TZC_NSAID_DEFAULT U(0) 317 318 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 319 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 320 321 /* 322 * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to 323 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as 324 * secure. The second and third regions gives non secure access to rest of DRAM. 325 */ 326 #define TC_TZC_REGIONS_DEF \ 327 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 328 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 329 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 330 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 331 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 332 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 333 334 /* virtual address used by dynamic mem_protect for chunk_base */ 335 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 336 337 #if ARM_GPT_SUPPORT 338 /* 339 * This overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT in board_css_def.h. 340 * Offset of the FIP in the GPT image. BL1 component uses this option 341 * as it does not load the partition table to get the FIP base 342 * address. At sector 48 for TC to align with ATU page size boundaries (8KiB) 343 * (i.e. after reserved sectors 0-47). 344 * Offset = 48 * 512 = 0x6000 345 */ 346 #undef PLAT_ARM_FIP_OFFSET_IN_GPT 347 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x6000 348 #endif /* ARM_GPT_SUPPORT */ 349 350 /* UART related constants */ 351 352 #undef PLAT_ARM_BOOT_UART_BASE 353 #define PLAT_ARM_BOOT_UART_BASE 0x2A410000 354 355 #undef PLAT_ARM_RUN_UART_BASE 356 #define PLAT_ARM_RUN_UART_BASE 0x2A400000 357 358 #undef PLAT_ARM_SP_MIN_RUN_UART_BASE 359 #define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE 360 361 #undef PLAT_ARM_CRASH_UART_BASE 362 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 363 364 #endif /* PLATFORM_DEF_H */ 365