1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/console.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 #include <imx8_lpuart.h> 23 #include <imx8ulp_caam.h> 24 #include <imx_plat_common.h> 25 #include <plat_imx8.h> 26 #include <upower_api.h> 27 28 #define MAP_BL31_TOTAL \ 29 MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE) 30 #define MAP_BL31_RO \ 31 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 32 33 #define MAP_COHERENT_MEM \ 34 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 static const mmap_region_t imx_mmap[] = { 38 DEVICE0_MAP, DEVICE1_MAP, ELE_MAP, 39 SEC_SIM_MAP, SRAM0_MAP, 40 {0} 41 }; 42 43 extern uint32_t upower_init(void); 44 extern void imx8ulp_init_scmi_server(void); 45 46 static entry_point_info_t bl32_image_ep_info; 47 static entry_point_info_t bl33_image_ep_info; 48 49 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 50 u_register_t arg2, u_register_t arg3) 51 { 52 static console_t console; 53 54 55 /* enable the GPIO D,E,F non-secure access by default */ 56 mmio_write_32(IMX_PCC4_BASE + 0x78, 0xc0000000); 57 mmio_write_32(IMX_PCC4_BASE + 0x7c, 0xc0000000); 58 mmio_write_32(IMX_PCC5_BASE + 0x114, 0xc0000000); 59 60 mmio_write_32(IMX_GPIOE_BASE + 0x10, 0xffffffff); 61 mmio_write_32(IMX_GPIOE_BASE + 0x14, 0x3); 62 mmio_write_32(IMX_GPIOE_BASE + 0x18, 0xffffffff); 63 mmio_write_32(IMX_GPIOE_BASE + 0x1c, 0x3); 64 65 mmio_write_32(IMX_GPIOF_BASE + 0x10, 0xffffffff); 66 mmio_write_32(IMX_GPIOF_BASE + 0x14, 0x3); 67 mmio_write_32(IMX_GPIOF_BASE + 0x18, 0xffffffff); 68 mmio_write_32(IMX_GPIOF_BASE + 0x1c, 0x3); 69 70 mmio_write_32(IMX_GPIOD_BASE + 0x10, 0xffffffff); 71 mmio_write_32(IMX_GPIOD_BASE + 0x14, 0x3); 72 mmio_write_32(IMX_GPIOD_BASE + 0x18, 0xffffffff); 73 mmio_write_32(IMX_GPIOD_BASE + 0x1c, 0x3); 74 75 console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 76 IMX_CONSOLE_BAUDRATE, &console); 77 78 /* This console is only used for boot stage */ 79 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 80 81 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 82 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry(); 83 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 84 } 85 86 void bl31_plat_arch_setup(void) 87 { 88 const mmap_region_t bl_regions[] = { 89 MAP_BL31_TOTAL, 90 MAP_BL31_RO, 91 #if USE_COHERENT_MEM 92 MAP_COHERENT_MEM, 93 #endif 94 {0}, 95 }; 96 97 setup_page_tables(bl_regions, imx_mmap); 98 enable_mmu_el3(0); 99 100 /* TODO: Hack, refine this piece, scmi channel free */ 101 mmio_write_32(SRAM0_BASE + 0x4, 1); 102 } 103 104 void bl31_platform_setup(void) 105 { 106 /* select the arch timer source */ 107 mmio_setbits_32(IMX_SIM1_BASE + 0x30, 0x8000000); 108 109 generic_delay_timer_init(); 110 111 plat_gic_driver_init(); 112 plat_gic_init(); 113 114 imx8ulp_init_scmi_server(); 115 upower_init(); 116 imx8ulp_caam_init(); 117 } 118 119 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 120 { 121 if (type == NON_SECURE) { 122 return &bl33_image_ep_info; 123 } else { 124 return &bl32_image_ep_info; 125 } 126 } 127 128 unsigned int plat_get_syscnt_freq2(void) 129 { 130 return COUNTER_FREQUENCY; 131 } 132 133 void bl31_plat_runtime_setup(void) 134 { 135 } 136