refactor(xilinx): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A

refactor(xilinx): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects Xilinx SoCs only.

Change-Id: Iea4cf920934bbde4312f40c8c7b3e0f56a316e86
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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refactor(mediatek): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-

refactor(mediatek): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the Mediatek platform only.

Change-Id: I83beee28ed856bc9b2f3131aa577be9bfa529028
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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refactor(armada): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A

refactor(armada): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch only affects the Armada SoC of Marvell's platform.

Change-Id: I7082fdb8c5507cd1ce5915d67e61e638605982e0
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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refactor(imx): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A pla

refactor(imx): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the Freescale/NXP SoCs imx93, imx8qm and imx8qx.

Change-Id: Iece74579e1d15eeeb8279db0c53d74bce45545bd
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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refactor(brcm): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A pl

refactor(brcm): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the Broadcom platform only.

Change-Id: I693f749bbf56911638b03e069659e86b95b1050e
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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Merge changes from topic "fix_psci_osi" into integration

* changes:
fix(psci): fix parent_idx in psci_validate_state_coordination
fix(psci): mask the Last in Level nibble in StateId

fix(xilinx): follow MISRA-C standards for condition check

As per the MISRA-C standards, there should be proc == NULL not just
!proc.

Fix the same.

Change-Id: I0e7650c09b045882a0235869d7ef9fca27f96

fix(xilinx): follow MISRA-C standards for condition check

As per the MISRA-C standards, there should be proc == NULL not just
!proc.

Fix the same.

Change-Id: I0e7650c09b045882a0235869d7ef9fca27f96d9a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(zynqmp): resolve null pointer dereferencing

The upstream coverity tool has reported the null pointer dereferences
(NULL_RETURNS) warning.

The coverity warning,
Dereferencing a pointer that migh

fix(zynqmp): resolve null pointer dereferencing

The upstream coverity tool has reported the null pointer dereferences
(NULL_RETURNS) warning.

The coverity warning,
Dereferencing a pointer that might be "NULL" "proc" when calling
"pm_client_suspend".

Fix the same by checking the NULL before processing further.

Change-Id: I33acead9250bab0ed24b94aa1c1bdc31e80de771
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge "chore: rename hermes to neoverse-n3" into integration

fix(psci): mask the Last in Level nibble in StateId

In the ARM recommended StateID Encoding, the index for the power
level where the calling core is last to go idle use the last niblle
of the StateI

fix(psci): mask the Last in Level nibble in StateId

In the ARM recommended StateID Encoding, the index for the power
level where the calling core is last to go idle use the last niblle
of the StateId.

Even if this nibble is necessary for OS-initiated mode, it can be
used by caller even when this OSI mode is not used.

In arm_validate_power_state() function, the StateId is compared with
content of arm_pm_idle_states[] build with the arm_make_pwrstate_lvl2
macro, without Last in Level information. So it is safe to mask this
nibble for ARM platform in all the cases, and that avoids issues with
caller with use the same StateId encoding with OSI mode activated or
not (in tftf tests for example, the input(power state) parameter =
(0x40001022) and the associated power state is 0x40000022).

Change-Id: I45e8e2b8f526fb61b94cf134d7d4aa3bac4c215d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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Merge changes from topic "makefile-cleanup" into integration

* changes:
build: improve diagnostics for unrecognized toolchain tools
build(rzg): separate BL2 and BL31 SREC generation
build(rcar

Merge changes from topic "makefile-cleanup" into integration

* changes:
build: improve diagnostics for unrecognized toolchain tools
build(rzg): separate BL2 and BL31 SREC generation
build(rcar): separate BL2 and BL31 SREC generation
build: separate preprocessing from DTB compilation
build: remove `MAKE_BUILD_STRINGS` function

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chore: rename hermes to neoverse-n3

Rename hermes cpu to Neoverse-N3

Change-Id: I912d4c824c5004a8c1909c68fef77f1f5e202b8a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge "fix(tc): enable FEAT_MTE2" into integration

Merge changes from topic "sm/feat_detect" into integration

* changes:
refactor(cpufeat): restore functions in detect_arch_features
refactor(cpufeat): add macro to simplify is_feat_xx_present
c

Merge changes from topic "sm/feat_detect" into integration

* changes:
refactor(cpufeat): restore functions in detect_arch_features
refactor(cpufeat): add macro to simplify is_feat_xx_present
chore: simplify the macro names in ENABLE_FEAT mechanism

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refactor(smccc): move pmf to vendor el3 calls

Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documenta

refactor(smccc): move pmf to vendor el3 calls

Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documentation 1.5:
https://developer.arm.com/documentation/den0028/latest

Add a deprecation notice to inform PMF is moved from arm-sip range to
vendor-specific EL3 range. PMF support from arm-sip range will be
removed and will not available after TF-A 2.12 release.

Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(smccc): move debugfs to vendor el3 calls

Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subrange

refactor(smccc): move debugfs to vendor el3 calls

Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subranges of Function identifiers to different services are:

0x87000000-0x8700FFFF-SMC32: Vendor-Specific EL3 Monitor Service Calls
0xC7000000-0xC700FFFF-SMC64: Vendor-Specific EL3 Monitor Service Calls

Amend Debugfs FID's to use this range and id.

Add a deprecation notice to inform debugfs moved from arm-sip range to
Vendor-Specific EL3 range. Debugfs support from arm-sip range will be
removed and will not be available after TF-A 2.12 release.

Reference to debugfs component level documentation:
https://trustedfirmware-a.readthedocs.io/en/latest/components/debugfs-design.html#overview

Change-Id: I97a50170178f361f70c95ed0049bc4e278de59d7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(fvp): move cpus with nomodel

Move CPUs which are not tested in CI under a new build option.
We have added some CPUs for which there is no FVP models available
yet to test. Move those CPUs u

refactor(fvp): move cpus with nomodel

Move CPUs which are not tested in CI under a new build option.
We have added some CPUs for which there is no FVP models available
yet to test. Move those CPUs under a new FVP build option.

Change-Id: I3da12d2f8d9c246b435b31adfac61c79dc1ab0cb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "build(fvp): make all builds unconditional" into integration

refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all th

refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:

-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability

The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.

- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.

Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "feat(zynqmp): remove unused pm_get_proc_by_node()" into integration

Merge "fix(xilinx): check proc variable before use" into integration

feat(zynqmp): remove unused pm_get_proc_by_node()

The pm_get_proc_by_node() is not used anywhere. Hence remove the
same.

Change-Id: Ifd68dd524cae0a9f1684d943019563027859ccea
Signed-off-by: Ronak Ja

feat(zynqmp): remove unused pm_get_proc_by_node()

The pm_get_proc_by_node() is not used anywhere. Hence remove the
same.

Change-Id: Ifd68dd524cae0a9f1684d943019563027859ccea
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor

Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via th

fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor

Add code that acknowledges all SoC interrupts and resets the Generic
Interrupt Controller before resetting the SoC via the Cortex-M3 secure
coprocessor.

Recall that Turris MOX has a HW bug wherein a SoC reset initiated by
writing the magic value to the North Bridge Warm Reset register may
randomly freeze the board.

Back in 2021 we introduced the CM3_SYSTEM_RESET build option for the
Armada 3700 platform, which, when enabled, adds code to the PSCI reset
handler so that the SoC reset is done by requesting the firmware in the
Cortex-M3 secure coprocessor to do it, instead of writing the Warm Reset
register.

The secure coprocessor firmware tried various things to put the board
into a state where the SoC reset circuit would work correctly. This
managed to fix the issue for some boards, but not for all of them.

Another considered method to overcome this issue was to reset all the
SoC peripheral controllers one by one by writing to specific registers,
instead of triggering the SoC reset circuit via the Warm Reset register.
This method was not used because until now, there was one peripheral
that I could not find a way how to reset properly: the Generic Interrupt
Controller (GIC).

After 3 years I have finally found a way how to reset the GIC, and it
needs to be done by the main processor, before the secure coprocessor
resets the main processor.

Change-Id: Icc23251ef97738b6b48af514d5118440ec21cdd7
Signed-off-by: Marek Behún <marek.behun@nic.cz>

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Merge "feat(mt8188): remove apusys kernel handler usage constraints" into integration

build(fvp): make all builds unconditional

commit@138221c2457b9d04101b84084c07d576b0eb5a51 reduced items that
should be build due to SRAM size limitations.

But newer models from 11.19 onwards suppor

build(fvp): make all builds unconditional

commit@138221c2457b9d04101b84084c07d576b0eb5a51 reduced items that
should be build due to SRAM size limitations.

But newer models from 11.19 onwards support to set SRAM size greater
than 256KB. So remove all dependency and conditional builds for FVP.

Change-Id: I38684e100450b74fdda0d685775e2cbce92170b6
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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