1 /* 2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/arm/css/css_mhu_doorbell.h> 14 #include <drivers/arm/css/scmi.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/arm/css/common/css_pm.h> 18 #include <plat/common/platform.h> 19 20 #include <nrd_ras.h> 21 #include <nrd_variant.h> 22 23 nrd_platform_info_t nrd_plat_info; 24 25 static scmi_channel_plat_info_t sgi575_scmi_plat_info = { 26 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 27 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, 28 .db_preserve_mask = 0xfffffffe, 29 .db_modify_mask = 0x1, 30 .ring_doorbell = &mhu_ring_doorbell, 31 }; 32 33 static scmi_channel_plat_info_t plat_rd_scmi_info[] = { 34 { 35 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 36 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0), 37 .db_preserve_mask = 0xfffffffe, 38 .db_modify_mask = 0x1, 39 .ring_doorbell = &mhuv2_ring_doorbell, 40 }, 41 #if (NRD_CHIP_COUNT > 1) 42 { 43 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 44 NRD_REMOTE_CHIP_MEM_OFFSET(1), 45 .db_reg_addr = PLAT_CSS_MHU_BASE 46 + NRD_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0), 47 .db_preserve_mask = 0xfffffffe, 48 .db_modify_mask = 0x1, 49 .ring_doorbell = &mhuv2_ring_doorbell, 50 }, 51 #endif 52 #if (NRD_CHIP_COUNT > 2) 53 { 54 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 55 NRD_REMOTE_CHIP_MEM_OFFSET(2), 56 .db_reg_addr = PLAT_CSS_MHU_BASE + 57 NRD_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0), 58 .db_preserve_mask = 0xfffffffe, 59 .db_modify_mask = 0x1, 60 .ring_doorbell = &mhuv2_ring_doorbell, 61 }, 62 #endif 63 #if (NRD_CHIP_COUNT > 3) 64 { 65 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE + 66 NRD_REMOTE_CHIP_MEM_OFFSET(3), 67 .db_reg_addr = PLAT_CSS_MHU_BASE + 68 NRD_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0), 69 .db_preserve_mask = 0xfffffffe, 70 .db_modify_mask = 0x1, 71 .ring_doorbell = &mhuv2_ring_doorbell, 72 }, 73 #endif 74 }; 75 76 static scmi_channel_plat_info_t plat3_rd_scmi_info[] = { 77 { 78 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 79 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 80 .db_preserve_mask = 0xfffffffe, 81 .db_modify_mask = 0x1, 82 .ring_doorbell = &mhu_ring_doorbell, 83 }, 84 }; 85 86 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id) 87 { 88 if (nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM || 89 nrd_plat_info.platform_id == RD_V1_SID_VER_PART_NUM || 90 nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM || 91 nrd_plat_info.platform_id == RD_V2_SID_VER_PART_NUM || 92 nrd_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM || 93 nrd_plat_info.platform_id == RD_N2_CFG3_SID_VER_PART_NUM) { 94 if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info)) { 95 panic(); 96 } 97 return &plat_rd_scmi_info[channel_id]; 98 } else if (nrd_plat_info.platform_id == RD_FREMONT_SID_VER_PART_NUM || 99 nrd_plat_info.platform_id == RD_FREMONT_CFG1_SID_VER_PART_NUM) { 100 if (channel_id >= ARRAY_SIZE(plat3_rd_scmi_info)) { 101 panic(); 102 } 103 return &plat3_rd_scmi_info[channel_id]; 104 } else if (nrd_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) { 105 return &sgi575_scmi_plat_info; 106 } else { 107 panic(); 108 } 109 } 110 111 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 112 u_register_t arg2, u_register_t arg3) 113 { 114 nrd_plat_info.platform_id = plat_arm_nrd_get_platform_id(); 115 nrd_plat_info.config_id = plat_arm_nrd_get_config_id(); 116 nrd_plat_info.multi_chip_mode = plat_arm_nrd_get_multi_chip_mode(); 117 118 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 119 } 120 121 void nrd_bl31_common_platform_setup(void) 122 { 123 generic_delay_timer_init(); 124 125 arm_bl31_platform_setup(); 126 127 /* Configure the warm reboot SGI for primary core */ 128 css_setup_cpu_pwr_down_intr(); 129 130 #if CSS_SYSTEM_GRACEFUL_RESET 131 /* Register priority level handlers for reboot */ 132 ehf_register_priority_handler(PLAT_REBOOT_PRI, 133 css_reboot_interrupt_handler); 134 #endif 135 } 136 137 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 138 { 139 /* 140 * For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are 141 * supported. 142 */ 143 if (((nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) && 144 (nrd_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) { 145 ops->cpu_standby = NULL; 146 ops->system_off = NULL; 147 ops->system_reset = NULL; 148 ops->get_sys_suspend_power_state = NULL; 149 ops->pwr_domain_suspend = NULL; 150 ops->pwr_domain_suspend_finish = NULL; 151 } 152 153 return css_scmi_override_pm_ops(ops); 154 } 155