refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory alloca

refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.

Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.

Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
rest

feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.

* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.

* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.

* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".

* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.

Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.

Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(qemu): exclude GPT reserve from BL32_MEM_SIZE

BL32_MEM_SIZE fails to take into account the space reserved for L0 and
L1 GPTs at the end of secure DRAM, when ENABLE_RME==1.

Fixes: cd75693f5ed3 (

fix(qemu): exclude GPT reserve from BL32_MEM_SIZE

BL32_MEM_SIZE fails to take into account the space reserved for L0 and
L1 GPTs at the end of secure DRAM, when ENABLE_RME==1.

Fixes: cd75693f5ed3 ("feat(qemu): setup memory map for RME")
Change-Id: If374b491d82be93c195cf501a9d12b9965d85182
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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fix(qemu): fix L0 GPT page table mapping

Page table mappings are missing the bitlock pages introduced by commit
e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock"). Add them to
the L0 mapping

fix(qemu): fix L0 GPT page table mapping

Page table mappings are missing the bitlock pages introduced by commit
e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock"). Add them to
the L0 mapping.

Change-Id: I6b63b9c6ea4bf01ab1fac98723340272babe7bf8
Reported-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Fixes: e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(versal): deprecate build time arg VERSAL_PLATFORM

Update Versal platform to enable runtime detection of variants instead
of relying on the build argument VERSAL_PLATFORM.
Integrate functionalit

feat(versal): deprecate build time arg VERSAL_PLATFORM

Update Versal platform to enable runtime detection of variants instead
of relying on the build argument VERSAL_PLATFORM.
Integrate functionality for identifying the board variant during
runtime, allowing dynamic adjustment of CPU and UART clock values
accordingly.
Print the runtime board information during boot.
This advancement streamlines the build process by eliminating
dependencies on variant-specific builds, enabling the use of a single
binary for multiple variants.
Removing all the platform related constants for versal_virt,SPP,EMU as
they are not used.

Change-Id: I8c1a1d391bd1a8971addc1f56f8309a3fb75aa6d
Signed-off-by: Amey Avinash Raghatate <AmeyAvinash.Raghatate@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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Merge "feat(handoff): fix register convention r1/x1 value on transfer list" into integration

Merge "feat(fgt2): add support for FEAT_FGT2" into integration

Merge changes from topic "us_dsu_pmu" into integration

* changes:
feat(tc): enable Last-level cache (LLC)
feat(cpus): add sysreg_bitfield_insert_from_gpr macro
feat(tc): add DSU PMU node for t

Merge changes from topic "us_dsu_pmu" into integration

* changes:
feat(tc): enable Last-level cache (LLC)
feat(cpus): add sysreg_bitfield_insert_from_gpr macro
feat(tc): add DSU PMU node for tc3
feat(tc): enable el1 access to DSU PMU registers
style(tc): remove comment for plat_reset_handler
fix(context-mgmt): keep actlr_el2 value in the init context

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feat(tc): enable Last-level cache (LLC)

The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.

This bit is not set for CPUs on TC3 platform de

feat(tc): enable Last-level cache (LLC)

The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.

This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.

Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "fix(arm): check the presence of the policy check function" into integration

fix(zynqmp): handle secure SGI at EL1 for OP-TEE

OP-TEE requires SGIs to be handled at S-EL1. The
Makefile was not properly setting the flag
GICV2_G0_FOR_EL3 to 0 when the SPD is OP-TEE.

Change-Id:

fix(zynqmp): handle secure SGI at EL1 for OP-TEE

OP-TEE requires SGIs to be handled at S-EL1. The
Makefile was not properly setting the flag
GICV2_G0_FOR_EL3 to 0 when the SPD is OP-TEE.

Change-Id: I256afa37ddf4ad4a154c43d51807de670c3689bb
Signed-off-by: Shen Jiamin <shen_jiamin@comp.nus.edu.sg>

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feat(spm): change UART0-1 to NS device region

To enable device memory sharing test make memory region for UART0
and 1 a NS device region so that it can be shared by tf-a-tests
to the cactus SP.

Sig

feat(spm): change UART0-1 to NS device region

To enable device memory sharing test make memory region for UART0
and 1 a NS device region so that it can be shared by tf-a-tests
to the cactus SP.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Iadfe02a65f5d4a8b60296f07c4943dd31f201453

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feat(tc): enable el1 access to DSU PMU registers

DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set

feat(tc): enable el1 access to DSU PMU registers

DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.

Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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style(tc): remove comment for plat_reset_handler

The comment for plat_reset_handler doesn't make sense. It is likely a
copy-and-paste error while adding the code, so remove it.

Change-Id: Iab8c8c79

style(tc): remove comment for plat_reset_handler

The comment for plat_reset_handler doesn't make sense. It is likely a
copy-and-paste error while adding the code, so remove it.

Change-Id: Iab8c8c799c184fa99966770d47ecb11bbc640515
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>

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Merge "fix(corstone1000): include platform header file" into integration

fix(corstone1000): include platform header file

Include platform.h file in order to remove following compiler errors,
as some warnings are being treated as errors now.
error: implicit declaration of

fix(corstone1000): include platform header file

Include platform.h file in order to remove following compiler errors,
as some warnings are being treated as errors now.
error: implicit declaration of function
'plat_core_pos_by_mpidr'[-Wimplicit-function-declaration]

Change-Id: Ie223e11e138ec9b0eef7342f450b90b215a49b15
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

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Merge "feat(debugv8p9): add support for FEAT_Debugv8p9" into integration

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was chang

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).

As updating of TL's signature, register value of x1/r1 should be:

In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).

Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.

This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.

2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.

This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).

Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705

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build: consolidate directory creation rules

This commit streamlines directory creation by introducing a single
pattern rule to automatically make directories for which there is a
dependency.

We cur

build: consolidate directory creation rules

This commit streamlines directory creation by introducing a single
pattern rule to automatically make directories for which there is a
dependency.

We currently use several macros to generate rules to create directories
upon dependence, which is a significant amount of code and a lot of
redundancy. The rule introduced by this change represents a catch-all:
any rule dependency on a path ending in a forward slash is automatically
created.

Now, rules can rely on an unordered dependency (`|`) on `$$(@D)/` which,
when secondary expansion is enabled, expands to the directory of the
target being built, e.g.:

build/main.o: main.c | $$(@D)/ # automatically creates `build/`

Change-Id: I7e554efa2ac850e779bb302fd9c7fbb239886c9f
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(intel): enable VAB support for Intel products

This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.

Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b

feat(intel): enable VAB support for Intel products

This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.

Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b3aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): add in SHA384 authentication

Add VAB SHA384 authentication implementation.

Change-Id: Ic22ab7416ffd0c514328d2815b136aa71ba96a84
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Sig

feat(intel): add in SHA384 authentication

Add VAB SHA384 authentication implementation.

Change-Id: Ic22ab7416ffd0c514328d2815b136aa71ba96a84
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update sip smc config addr for agilex5

Agilex5 DDR base address started from 0x8000 0000.
Thus the SIP_SMC_FPGA_CONFIG_ADDR shall be offset to
0x8040 0000.

Change-Id: I33a840cb8ebbe02bc

fix(intel): update sip smc config addr for agilex5

Agilex5 DDR base address started from 0x8000 0000.
Thus the SIP_SMC_FPGA_CONFIG_ADDR shall be offset to
0x8040 0000.

Change-Id: I33a840cb8ebbe02bc7ff9b1f5d452641af11e576
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge changes If8547b5a,I6826a56d,Idb40907a,Ia51cbe1a,I9b55f6c5, ... into integration

* changes:
feat(fvp): add SPM manifest for OP-TEE at S-EL1 without S-EL2/Hafnium
fix(fvp): update the memory

Merge changes If8547b5a,I6826a56d,Idb40907a,Ia51cbe1a,I9b55f6c5, ... into integration

* changes:
feat(fvp): add SPM manifest for OP-TEE at S-EL1 without S-EL2/Hafnium
fix(fvp): update the memory size allocated to optee at EL1
fix(fvp): add DRAM memory regions that linux kernel can share
feat(fvp): update FF-A version to v1.1 supported by optee
feat(fvp): replace managed-exit with ns-interrupts-action
fix(fvp): add optee specific mem-size attribute
fix(fvp): fix the FF-A optee manifest by adding the boot info node

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fix(intel): software workaround for bridge timeout

Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.

Change-Id

fix(intel): software workaround for bridge timeout

Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.

Change-Id: I78d8ee0596c3e7bd4883bfd6e92c883b8e369c10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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