1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #include "../stm32mp2_def.h" 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #define PLATFORM_STACK_SIZE 0xC00 22 23 #define STM32MP_PRIMARY_CPU U(0x0) 24 #define STM32MP_SECONDARY_CPU U(0x1) 25 26 #define MAX_IO_DEVICES U(4) 27 #define MAX_IO_HANDLES U(4) 28 #define MAX_IO_BLOCK_DEVICES U(1) 29 #define MAX_IO_MTD_DEVICES U(1) 30 31 #define PLATFORM_CLUSTER_COUNT U(1) 32 #define PLATFORM_CORE_COUNT U(2) 33 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(2) 34 35 #define PLAT_MAX_PWR_LVL U(5) 36 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL U(5) 37 #define PLAT_NUM_PWR_DOMAINS U(7) 38 39 /* Local power state for power domains in Run state. */ 40 #define STM32MP_LOCAL_STATE_RUN U(0) 41 /* Local power state for retention. */ 42 #define STM32MP_LOCAL_STATE_RET U(1) 43 #define STM32MP_LOCAL_STATE_LP U(2) 44 #define PLAT_MAX_RET_STATE STM32MP_LOCAL_STATE_LP 45 /* Local power state for OFF/power-down. */ 46 #define STM32MP_LOCAL_STATE_OFF U(3) 47 #define PLAT_MAX_OFF_STATE STM32MP_LOCAL_STATE_OFF 48 49 /* Macros to parse the state information from State-ID (recommended encoding) */ 50 #define PLAT_LOCAL_PSTATE_WIDTH U(4) 51 #define PLAT_LOCAL_PSTATE_MASK GENMASK(PLAT_LOCAL_PSTATE_WIDTH - 1U, 0) 52 53 /******************************************************************************* 54 * BL2 specific defines. 55 ******************************************************************************/ 56 /* 57 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 58 * size plus a little space for growth. 59 */ 60 #define BL2_BASE STM32MP_BL2_BASE 61 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 62 STM32MP_BL2_SIZE) 63 64 #define BL2_RO_BASE STM32MP_BL2_RO_BASE 65 #define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \ 66 STM32MP_BL2_RO_SIZE) 67 68 #define BL2_RW_BASE STM32MP_BL2_RW_BASE 69 #define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \ 70 STM32MP_BL2_RW_SIZE) 71 72 /******************************************************************************* 73 * BL31 specific defines. 74 ******************************************************************************/ 75 #define BL31_BASE 0 76 #define BL31_LIMIT STM32MP_BL31_SIZE 77 78 /******************************************************************************* 79 * BL33 specific defines. 80 ******************************************************************************/ 81 #define BL33_BASE STM32MP_BL33_BASE 82 83 /******************************************************************************* 84 * DTB specific defines. 85 ******************************************************************************/ 86 #define DTB_BASE STM32MP_DTB_BASE 87 #define DTB_LIMIT (STM32MP_DTB_BASE + \ 88 STM32MP_DTB_SIZE) 89 90 /******************************************************************************* 91 * Platform specific page table and MMU setup constants 92 ******************************************************************************/ 93 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 33) 94 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 33) 95 96 /******************************************************************************* 97 * Declarations and constants to access the mailboxes safely. Each mailbox is 98 * aligned on the biggest cache line size in the platform. This is known only 99 * to the platform as it might have a combination of integrated and external 100 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 101 * line at any cache level. They could belong to different cpus/clusters & 102 * get written while being protected by different locks causing corruption of 103 * a valid mailbox address. 104 ******************************************************************************/ 105 #define CACHE_WRITEBACK_SHIFT 6 106 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 107 108 #endif /* PLATFORM_DEF_H */ 109