feat(stm32mp2): handle DDR power supplies

Modify platform driver to handle the DDR power supplies when
a PMIC is present.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I98df132a63c2ad

feat(stm32mp2): handle DDR power supplies

Modify platform driver to handle the DDR power supplies when
a PMIC is present.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I98df132a63c2ad351d4dae949f5dbb831cc40637

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feat(stm32mp1): handle DDR power supplies

Modify the DDR driver to handle the DDR power supplies when a PMIC
is present in the function stm32mp_board_ddr_power_init(), define
in the platform file.

feat(stm32mp1): handle DDR power supplies

Modify the DDR driver to handle the DDR power supplies when a PMIC
is present in the function stm32mp_board_ddr_power_init(), define
in the platform file.

This patch allows to easily modify the used DDR power supplies
for customer boards, when they don't use STPMIC1 PMU or when
the regulators are not connected as on the STMicroelectronics
boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I93ee6295ef7032ac20f03608d22cd460f7d87ef5

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Merge changes I1df23bfa,Ibc85e30c into integration

* changes:
fix(st): support device tree DDR sizes higher than 16Gbits for aarch64
feat(fdt-wrappers): add function to read uint64 with default

Merge changes I1df23bfa,Ibc85e30c into integration

* changes:
fix(st): support device tree DDR sizes higher than 16Gbits for aarch64
feat(fdt-wrappers): add function to read uint64 with default value

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Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL

Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL31 for RD-1 AE platform
feat(rd1ae): add device tree files
feat(rd1ae): introduce Arm RD-1 AE platform
build(bl2): enable check for bl2 base overflow assert
feat(arm): add support for loading CONFIG from BL2

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fix(versal2): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-I

fix(versal2): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: Iee222595962273913a570786ff1df5dc3ad328df
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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fix(versal-net): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Chang

fix(versal-net): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I20ef3be35f88649979d577ec8be4357813d4c1b7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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fix(versal): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id

fix(versal): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: If3507f812ed4cfa518e6f5c5de977a76713fafd8
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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fix(xilinx): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id

fix(xilinx): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I1d369d977e0f2749024736d53fbb5c7d5555f6cb
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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fix(zynqmp): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id

fix(zynqmp): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I435dbcbe1c4aad7c69eb49599cd0dbca0677150d
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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Merge "build: make Poetry optional" into integration

Merge changes from topic "nxp-s32g274a/err051700" into integration

* changes:
feat(s32g274a): enable workaround for ERR051700
fix(s32g274a): workaround for ERR051700 erratum

feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE

In this commit, Trusted Board Boot has been enabled for the RD-1 AE
platform, and the non-volatile counter remains at the default
values sin

feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE

In this commit, Trusted Board Boot has been enabled for the RD-1 AE
platform, and the non-volatile counter remains at the default
values since the non-volatile counter is read-only for Arm
development platforms.

Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I2e1072101e56da0e474d2a3e9802e5d65a77fd55

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feat(rd1ae): introduce BL31 for RD-1 AE platform

This commit introduces BL31 to the RD-1 AE platform. The RD-1 AE
platform incorporates an SCP for CPU power control.

Additinaly introducing the memo

feat(rd1ae): introduce BL31 for RD-1 AE platform

This commit introduces BL31 to the RD-1 AE platform. The RD-1 AE
platform incorporates an SCP for CPU power control.

Additinaly introducing the memory descriptor provides BL image
information that gets used by BL2 to load the images

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I035cbfd09f254aa47483ad35676f1cb3ffb661bd

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feat(rd1ae): add device tree files

This commit Add FW_CONFIG and HW_CONFIG device trees

Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: Ia6cbf06def8ec9b74ef9040bab801278a3117899

feat(rd1ae): introduce Arm RD-1 AE platform

Create a new platform for the RD-1 AE automotive FVP.
This platform contains:
* Neoverse-V3AE, Arm9.2-A application processor
* A GICv4-compatible GIC-7

feat(rd1ae): introduce Arm RD-1 AE platform

Create a new platform for the RD-1 AE automotive FVP.
This platform contains:
* Neoverse-V3AE, Arm9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 1 MB is reserved for TF-A

and BL2 runs at ELmax (EL3).

Additionally, this commit updates the maintainers.rst file and
the changelog.yaml to add scope for RD-1 AE variants.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
Signed-off-by: Rahul Singh <rahul.singh@arm.com>
Change-Id: I9ae64b3f05a52653ebd1d334b15b7f21821264e2

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build(bl2): enable check for bl2 base overflow assert

Currently, the BL2 base overflow check asserts for all cases,
but this check is only necessary if not reset to BL2 case.
Therefore, adding a con

build(bl2): enable check for bl2 base overflow assert

Currently, the BL2 base overflow check asserts for all cases,
but this check is only necessary if not reset to BL2 case.
Therefore, adding a condition for this check.

Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: Ia129921d76bcd32058ea0767db0319e6724be8ab

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feat(arm): add support for loading CONFIG from BL2

This commit introduces a new ARM platform-specific build option called
`ARM_FW_CONFIG_LOAD_ENABLE`. This option enables the loading of the
`fw_conf

feat(arm): add support for loading CONFIG from BL2

This commit introduces a new ARM platform-specific build option called
`ARM_FW_CONFIG_LOAD_ENABLE`. This option enables the loading of the
`fw_config` device tree when resetting to the BL2 scenario.

Additionally, the FW_CONFIG image reference has been added to the
fdts/tbbr_cot_descriptors.dtsi file in order to use in the scenario of
RESET_TO_BL2.

Signed-off-by: Divin Raj <divin.raj@arm.com>
Change-Id: I11de497b7dbb1386ed84d939d6fd2a11856e9e1b

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Merge changes from topic "rd-v3-reset-to-bl31" into integration

* changes:
feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

Merge changes from topic "rd-v3-reset-to-bl31" into integration

* changes:
feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms
feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow
feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3
feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

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build: make Poetry optional

The Yocto team has requested that we do not use Poetry from within the
Makefile, as Yocto does not have network access during the build
process.

We want to maintain the

build: make Poetry optional

The Yocto team has requested that we do not use Poetry from within the
Makefile, as Yocto does not have network access during the build
process.

We want to maintain the current behaviour, so this change makes our use
of Poetry contigent on it being available in the environment.

Additionally, explicitly passing an empty toolchain parameter now allows
a tool to be *disabled* (e.g. passing `POETRY=` will prevent the build
system from trying to use Poetry).

Change-Id: Ibf552a3fee1eaadee767a1b948b559700083b401
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(xilinx): fix comment about MEM_BASE/SIZE

Comment is not showing correct macro name that's why fix it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I8bc38534309285af8a27ee43782e

fix(xilinx): fix comment about MEM_BASE/SIZE

Comment is not showing correct macro name that's why fix it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I8bc38534309285af8a27ee43782e03e9d0470267

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fix(intel): update CCU configuration for Agilex5 platform

Update CCU configuration for DSU, FPGA2SOC, GIC_M, SMMU, PSS NOC, DCE0,
DCE1,DMI0, DMI1, L4 peripheral firewall, L4 system firewall, LWSOC2F

fix(intel): update CCU configuration for Agilex5 platform

Update CCU configuration for DSU, FPGA2SOC, GIC_M, SMMU, PSS NOC, DCE0,
DCE1,DMI0, DMI1, L4 peripheral firewall, L4 system firewall, LWSOC2FPGA,
SOCFPGA and TCU.

Change-Id: Id416d58b0115098b99a8dfdccb28a7d6f6747f75
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(s32g274a): enable workaround for ERR051700

ERR051700 erratum applies to all S32G274A chip revisions; therefore,
it is enabled for the S32G274ARDB2 board.

Change-Id: I1ec436e99bc9328e42e74aef9d

feat(s32g274a): enable workaround for ERR051700

ERR051700 erratum applies to all S32G274A chip revisions; therefore,
it is enabled for the S32G274ARDB2 board.

Change-Id: I1ec436e99bc9328e42e74aef9d93f18e0f82bd7a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneo

fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneously, may cause a false error in the fault control
unit.

The workaround is to clear the SRD resets sequentially instead of
simultaneously.

Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "dynamic-toolchain" into integration

* changes:
build: allow multiple toolchain defaults
build: determine toolchain tools dynamically

feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms

Allow building RESET_TO_BL31 for third generation neoverse-rd
platforms.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subra

feat(neoverse-rd): allow RESET_TO_BL31 for third gen platforms

Allow building RESET_TO_BL31 for third generation neoverse-rd
platforms.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I30256969e5671043b3e58c76922985f7252429af

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