| #
33667d29 |
| 30-Aug-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().
Change-Id:
feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().
Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
show more ...
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| #
f480c9c4 |
| 17-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(stm32mp1): correct include order" into integration
|
| #
ff7675eb |
| 17-Dec-2021 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.
Change-Id: Iaca959add924e0e1fa2e56fab2348f0e
fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.
Change-Id: Iaca959add924e0e1fa2e56fab2348f0ee36e5fa7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| #
4abb0db1 |
| 14-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st_uart_update" into integration
* changes:
feat(st): protect UART during platform init
feat(stm32mp1): update console management for SP_min
refactor(stm32mp1): impro
Merge changes from topic "st_uart_update" into integration
* changes:
feat(st): protect UART during platform init
feat(stm32mp1): update console management for SP_min
refactor(stm32mp1): improve console management in BL2
feat(plat/st): add a function to configure console
feat(stm32mp1): add stm32_get_boot_interface function
refactor(stm32mp1): move stm32_save_boot_interface()
fix(stm32mp1): deconfigure UART RX pins
feat(stm32_gpio): add a function to reset a pin
refactor(stm32mp1): sort compilation flags
feat(stm32mp1): add sign-compare warning
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| #
acf28c26 |
| 18-Oct-2021 |
Yann Gautier <yann.gautier@st.com> |
feat(st): protect UART during platform init
Protect the UART instance used for serial boot
with UART used for console.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ieee1557b
feat(st): protect UART during platform init
Protect the UART instance used for serial boot
with UART used for console.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ieee1557b34e7baa81594c3fbf0513191737027bf
show more ...
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| #
a6bfa75c |
| 16-Dec-2020 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): add stm32_get_boot_interface function
Add function stm32_get_boot_interface to get the current boot interface
from information saved in the TAMP register.
Change-Id: I23af43c68eeaeb
feat(stm32mp1): add stm32_get_boot_interface function
Add function stm32_get_boot_interface to get the current boot interface
from information saved in the TAMP register.
Change-Id: I23af43c68eeaebe4c45920a57d739117aea3fbb1
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
show more ...
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| #
4dc77a35 |
| 10-Dec-2021 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): move stm32_save_boot_interface()
The function stm32_save_boot_interface()is moved to stm32mp1_private.c
file. The files stm32mp1_context.{c,h} are removed.
As return is always 0,
refactor(stm32mp1): move stm32_save_boot_interface()
The function stm32_save_boot_interface()is moved to stm32mp1_private.c
file. The files stm32mp1_context.{c,h} are removed.
As return is always 0, change the function to return void.
Call it earlier, to be able to use it when configuring console.
Change-Id: I8986e1257dc8e8708eab044a51ea1f2426b16597
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| #
d7176f03 |
| 04-Jun-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
fix(stm32mp1): deconfigure UART RX pins
Those pins are configured by ROM code, for serial boot use cases.
Their configs are reset if the boot is done on UART, but not on USB.
This should then be don
fix(stm32mp1): deconfigure UART RX pins
Those pins are configured by ROM code, for serial boot use cases.
Their configs are reset if the boot is done on UART, but not on USB.
This should then be done in TF-A. This has to be done after clock
init, and before console is configured.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I29a9694e25fcf1665360dd71f73937f769c43b52
show more ...
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| #
737ad29b |
| 11-Jun-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32_gpio): add a function to reset a pin
Add set_gpio_reset_cfg() to set a pin in its reset configuration:
analog, no-pull, speed low, and its secure configuration, thanks to
stm32_gpio_is_se
feat(stm32_gpio): add a function to reset a pin
Add set_gpio_reset_cfg() to set a pin in its reset configuration:
analog, no-pull, speed low, and its secure configuration, thanks to
stm32_gpio_is_secure_at_reset().
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b73c3636859f97fcc57f81cf68b42efc727922e
show more ...
|
| #
7c621113 |
| 06-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st_uart" into integration
* changes:
feat(plat/st): add STM32MP_UART_PROGRAMMER target
feat(plat/st): add STM32CubeProgrammer support on UART
feat(drivers/st/uart): a
Merge changes from topic "st_uart" into integration
* changes:
feat(plat/st): add STM32MP_UART_PROGRAMMER target
feat(plat/st): add STM32CubeProgrammer support on UART
feat(drivers/st/uart): add uart driver for STM32MP1
show more ...
|
| #
9083fa11 |
| 28-Oct-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
feat(plat/st): add STM32MP_UART_PROGRAMMER target
Handle boot from UART with STM32CubeProgammer based on mmap io
for STM32MP15.
Depends-On: Iba84e8dfd67b9f30416efb0f6778e48ba1f75dad
Signed-off-by:
feat(plat/st): add STM32MP_UART_PROGRAMMER target
Handle boot from UART with STM32CubeProgammer based on mmap io
for STM32MP15.
Depends-On: Iba84e8dfd67b9f30416efb0f6778e48ba1f75dad
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ibd719dd46a11da78633728675ef6639635b6cf67
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| #
2ed0c59b |
| 09-Sep-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(plat/st): add a new DDR firewall management" into integration
|
| #
4584e01d |
| 27-Sep-2020 |
Lionel Debieve <lionel.debieve@st.com> |
feat(plat/st): add a new DDR firewall management
Based on FCONF framework, define DDR firewall regions
from firmware config file instead of static defines.
Change-Id: I471e15410ca286d9079a86e3dc347
feat(plat/st): add a new DDR firewall management
Based on FCONF framework, define DDR firewall regions
from firmware config file instead of static defines.
Change-Id: I471e15410ca286d9079a86e3dc3474f66d37b5ab
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| #
2a008779 |
| 16-Jun-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "soc_id" into integration
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
fea
Merge changes from topic "soc_id" into integration
* changes:
refactor(plat/nvidia): use SOC_ID defines
refactor(plat/mediatek): use SOC_ID defines
refactor(plat/arm): use SOC_ID defines
feat(plat/st): implement platform functions for SMCCC_ARCH_SOC_ID
refactor(plat/st): export functions to get SoC information
feat(smccc): add bit definition for SMCCC_ARCH_SOC_ID
show more ...
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| #
92661e01 |
| 10-May-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(plat/st): export functions to get SoC information
Three functions are exported to get SoC version, SoC device ID, and SoC
name. Those functions are based on reworked existing static functio
refactor(plat/st): export functions to get SoC information
Three functions are exported to get SoC version, SoC device ID, and SoC
name. Those functions are based on reworked existing static functions.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1f3949062bb488286a9e7a38ffcd1457953dac56
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| #
5dfe680f |
| 14-Oct-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "stm32mp1: use %u in NOTICE message for board info" into integration
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| #
ab049ec0 |
| 13-Oct-2020 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: use %u in NOTICE message for board info
The board information values, read in an OTP are never negative,
%u is then used instead of %d.
Change-Id: I3bc22401fb4d54666ddf56411f75b79aca73849
stm32mp1: use %u in NOTICE message for board info
The board information values, read in an OTP are never negative,
%u is then used instead of %d.
Change-Id: I3bc22401fb4d54666ddf56411f75b79aca738492
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
80d9cf78 |
| 13-Oct-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "stm32mp1_plat_updates" into integration
* changes:
docs: update STM32MP1 with versions details
stm32mp1: get peripheral base address from a define
stm32mp1: add finis
Merge changes from topic "stm32mp1_plat_updates" into integration
* changes:
docs: update STM32MP1 with versions details
stm32mp1: get peripheral base address from a define
stm32mp1: add finished good variant in board identifier
show more ...
|
| #
113e8fda |
| 13-Oct-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "stm32mp1: add asserts in get_cpu_package() and get_part_number()" into integration
|
| #
5d51036c |
| 13-Oct-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "stm32mp1: add support for new SoC profiles" into integration
|
| #
0e935f00 |
| 13-Oct-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "stm32mp1: support of STM32MP15x Rev.Z" into integration
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| #
d75a3409 |
| 23-Sep-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
stm32mp1: add asserts in get_cpu_package() and get_part_number()
Change-Id: I2b702698d6be93da5ac86da1cbc98b3838315a5a
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Ga
stm32mp1: add asserts in get_cpu_package() and get_part_number()
Change-Id: I2b702698d6be93da5ac86da1cbc98b3838315a5a
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
8ccf4954 |
| 17-May-2019 |
Lionel Debieve <lionel.debieve@st.com> |
stm32mp1: add support for new SoC profiles
Update to support new part numbers.
Add new STM32 MPUs Part = STM32MP151F, STM32MP153F, STM32MP157F,
STM32MP151D, STM32MP153D, STM32MP157D
The STM32MP1 s
stm32mp1: add support for new SoC profiles
Update to support new part numbers.
Add new STM32 MPUs Part = STM32MP151F, STM32MP153F, STM32MP157F,
STM32MP151D, STM32MP153D, STM32MP157D
The STM32MP1 series is available in 3 different lines which are pin-to-pin
compatible:
- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz,
3D GPU, DSI display interface and CAN FD
- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz
and CAN FD
- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
Each line comes with a security option (cryptography & secure boot)
& a Cortex-A frequency option :
- A Basic + Cortex-A7 @ 650 MHz
- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D Basic + Cortex-A7 @ 800 MHz
- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
Remove useless variable in stm32mp_is_single_core().
Change-Id: Id30c836af986c6340c91efa8a7ae9480a2827089
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
ffb3f277 |
| 25-Jun-2019 |
Lionel Debieve <lionel.debieve@st.com> |
stm32mp1: support of STM32MP15x Rev.Z
Add a new revision of STM32MP15x CPU (Rev.Z).
Change-Id: I227dd6d9b3fcc43270015cfb21f60aeb0a8ab658
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed
stm32mp1: support of STM32MP15x Rev.Z
Add a new revision of STM32MP15x CPU (Rev.Z).
Change-Id: I227dd6d9b3fcc43270015cfb21f60aeb0a8ab658
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
f964f5c3 |
| 08-Jan-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
stm32mp1: add finished good variant in board identifier
Update the board info with the new coding including the finished good
variant:
Board: MBxxxx Var<CPN>.<FG> Rev.<Rev>-<BOM>
The OTP 59 coding
stm32mp1: add finished good variant in board identifier
Update the board info with the new coding including the finished good
variant:
Board: MBxxxx Var<CPN>.<FG> Rev.<Rev>-<BOM>
The OTP 59 coding is:
bit [31:16] (hex) => MBxxxx
bit [15:12] (dec) => Variant CPN (1....15)
bit [11:8] (dec) => Revision board (index with A = 1, Z = 26)
bit [7:4] (dec) => Variant FG : finished good (NEW)
bit [3:0] (dec) => BOM (01, .... 255)
Change-Id: I4fbc0c84596419d1bc30d166311444ece1d9123f
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
|