1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <drivers/st/stm32_iwdg.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 16 /* Internal layout of the 32bit OTP word board_id */ 17 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 18 #define BOARD_ID_BOARD_NB_SHIFT 16 19 #define BOARD_ID_VARIANT_MASK GENMASK(15, 12) 20 #define BOARD_ID_VARIANT_SHIFT 12 21 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 22 #define BOARD_ID_REVISION_SHIFT 8 23 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 24 25 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 26 BOARD_ID_BOARD_NB_SHIFT) 27 #define BOARD_ID2VAR(_id) (((_id) & BOARD_ID_VARIANT_MASK) >> \ 28 BOARD_ID_VARIANT_SHIFT) 29 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 30 BOARD_ID_REVISION_SHIFT) 31 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 32 33 #if defined(IMAGE_BL2) 34 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 35 STM32MP_SYSRAM_SIZE, \ 36 MT_MEMORY | \ 37 MT_RW | \ 38 MT_SECURE | \ 39 MT_EXECUTE_NEVER) 40 #elif defined(IMAGE_BL32) 41 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 42 STM32MP_SEC_SYSRAM_SIZE, \ 43 MT_MEMORY | \ 44 MT_RW | \ 45 MT_SECURE | \ 46 MT_EXECUTE_NEVER) 47 48 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 49 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 50 STM32MP_NS_SYSRAM_SIZE, \ 51 MT_DEVICE | \ 52 MT_RW | \ 53 MT_NS | \ 54 MT_EXECUTE_NEVER) 55 #endif 56 57 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 58 STM32MP1_DEVICE1_SIZE, \ 59 MT_DEVICE | \ 60 MT_RW | \ 61 MT_SECURE | \ 62 MT_EXECUTE_NEVER) 63 64 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 65 STM32MP1_DEVICE2_SIZE, \ 66 MT_DEVICE | \ 67 MT_RW | \ 68 MT_SECURE | \ 69 MT_EXECUTE_NEVER) 70 71 #if defined(IMAGE_BL2) 72 static const mmap_region_t stm32mp1_mmap[] = { 73 MAP_SEC_SYSRAM, 74 MAP_DEVICE1, 75 MAP_DEVICE2, 76 {0} 77 }; 78 #endif 79 #if defined(IMAGE_BL32) 80 static const mmap_region_t stm32mp1_mmap[] = { 81 MAP_SEC_SYSRAM, 82 MAP_NS_SYSRAM, 83 MAP_DEVICE1, 84 MAP_DEVICE2, 85 {0} 86 }; 87 #endif 88 89 void configure_mmu(void) 90 { 91 mmap_add(stm32mp1_mmap); 92 init_xlat_tables(); 93 94 enable_mmu_svc_mon(0); 95 } 96 97 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 98 { 99 if (bank == GPIO_BANK_Z) { 100 return GPIOZ_BASE; 101 } 102 103 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 104 105 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 106 } 107 108 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 109 { 110 if (bank == GPIO_BANK_Z) { 111 return 0; 112 } 113 114 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 115 116 return bank * GPIO_BANK_OFFSET; 117 } 118 119 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 120 { 121 if (bank == GPIO_BANK_Z) { 122 return GPIOZ; 123 } 124 125 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 126 127 return GPIOA + (bank - GPIO_BANK_A); 128 } 129 130 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 131 { 132 switch (bank) { 133 case GPIO_BANK_A: 134 case GPIO_BANK_B: 135 case GPIO_BANK_C: 136 case GPIO_BANK_D: 137 case GPIO_BANK_E: 138 case GPIO_BANK_F: 139 case GPIO_BANK_G: 140 case GPIO_BANK_H: 141 case GPIO_BANK_I: 142 case GPIO_BANK_J: 143 case GPIO_BANK_K: 144 return fdt_path_offset(fdt, "/soc/pin-controller"); 145 case GPIO_BANK_Z: 146 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 147 default: 148 panic(); 149 } 150 } 151 152 static int get_part_number(uint32_t *part_nb) 153 { 154 uint32_t part_number; 155 uint32_t dev_id; 156 157 assert(part_nb != NULL); 158 159 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 160 return -1; 161 } 162 163 if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { 164 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 165 return -1; 166 } 167 168 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 169 PART_NUMBER_OTP_PART_SHIFT; 170 171 *part_nb = part_number | (dev_id << 16); 172 173 return 0; 174 } 175 176 static int get_cpu_package(uint32_t *cpu_package) 177 { 178 uint32_t package; 179 180 assert(cpu_package != NULL); 181 182 if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { 183 ERROR("BSEC: PACKAGE_OTP Error\n"); 184 return -1; 185 } 186 187 *cpu_package = (package & PACKAGE_OTP_PKG_MASK) >> 188 PACKAGE_OTP_PKG_SHIFT; 189 190 return 0; 191 } 192 193 void stm32mp_print_cpuinfo(void) 194 { 195 const char *cpu_s, *cpu_r, *pkg; 196 uint32_t part_number; 197 uint32_t cpu_package; 198 uint32_t chip_dev_id; 199 int ret; 200 201 /* MPUs Part Numbers */ 202 ret = get_part_number(&part_number); 203 if (ret < 0) { 204 WARN("Cannot get part number\n"); 205 return; 206 } 207 208 switch (part_number) { 209 case STM32MP157C_PART_NB: 210 cpu_s = "157C"; 211 break; 212 case STM32MP157A_PART_NB: 213 cpu_s = "157A"; 214 break; 215 case STM32MP153C_PART_NB: 216 cpu_s = "153C"; 217 break; 218 case STM32MP153A_PART_NB: 219 cpu_s = "153A"; 220 break; 221 case STM32MP151C_PART_NB: 222 cpu_s = "151C"; 223 break; 224 case STM32MP151A_PART_NB: 225 cpu_s = "151A"; 226 break; 227 case STM32MP157F_PART_NB: 228 cpu_s = "157F"; 229 break; 230 case STM32MP157D_PART_NB: 231 cpu_s = "157D"; 232 break; 233 case STM32MP153F_PART_NB: 234 cpu_s = "153F"; 235 break; 236 case STM32MP153D_PART_NB: 237 cpu_s = "153D"; 238 break; 239 case STM32MP151F_PART_NB: 240 cpu_s = "151F"; 241 break; 242 case STM32MP151D_PART_NB: 243 cpu_s = "151D"; 244 break; 245 default: 246 cpu_s = "????"; 247 break; 248 } 249 250 /* Package */ 251 ret = get_cpu_package(&cpu_package); 252 if (ret < 0) { 253 WARN("Cannot get CPU package\n"); 254 return; 255 } 256 257 switch (cpu_package) { 258 case PKG_AA_LFBGA448: 259 pkg = "AA"; 260 break; 261 case PKG_AB_LFBGA354: 262 pkg = "AB"; 263 break; 264 case PKG_AC_TFBGA361: 265 pkg = "AC"; 266 break; 267 case PKG_AD_TFBGA257: 268 pkg = "AD"; 269 break; 270 default: 271 pkg = "??"; 272 break; 273 } 274 275 /* REVISION */ 276 ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id); 277 if (ret < 0) { 278 WARN("Cannot get CPU version\n"); 279 return; 280 } 281 282 switch (chip_dev_id) { 283 case STM32MP1_REV_B: 284 cpu_r = "B"; 285 break; 286 case STM32MP1_REV_Z: 287 cpu_r = "Z"; 288 break; 289 default: 290 cpu_r = "?"; 291 break; 292 } 293 294 NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r); 295 } 296 297 void stm32mp_print_boardinfo(void) 298 { 299 uint32_t board_id; 300 uint32_t board_otp; 301 int bsec_node, bsec_board_id_node; 302 void *fdt; 303 const fdt32_t *cuint; 304 305 if (fdt_get_address(&fdt) == 0) { 306 panic(); 307 } 308 309 bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); 310 if (bsec_node < 0) { 311 return; 312 } 313 314 bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); 315 if (bsec_board_id_node <= 0) { 316 return; 317 } 318 319 cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); 320 if (cuint == NULL) { 321 panic(); 322 } 323 324 board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); 325 326 if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { 327 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 328 return; 329 } 330 331 if (board_id != 0U) { 332 char rev[2]; 333 334 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 335 rev[1] = '\0'; 336 NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n", 337 BOARD_ID2NB(board_id), 338 BOARD_ID2VAR(board_id), 339 rev, 340 BOARD_ID2BOM(board_id)); 341 } 342 } 343 344 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 345 bool stm32mp_is_single_core(void) 346 { 347 uint32_t part_number; 348 349 if (get_part_number(&part_number) < 0) { 350 ERROR("Invalid part number, assume single core chip"); 351 return true; 352 } 353 354 switch (part_number) { 355 case STM32MP151A_PART_NB: 356 case STM32MP151C_PART_NB: 357 case STM32MP151D_PART_NB: 358 case STM32MP151F_PART_NB: 359 return true; 360 361 default: 362 return false; 363 } 364 } 365 366 /* Return true when device is in closed state */ 367 bool stm32mp_is_closed_device(void) 368 { 369 uint32_t value; 370 371 if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || 372 (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { 373 return true; 374 } 375 376 return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; 377 } 378 379 uint32_t stm32_iwdg_get_instance(uintptr_t base) 380 { 381 switch (base) { 382 case IWDG1_BASE: 383 return IWDG1_INST; 384 case IWDG2_BASE: 385 return IWDG2_INST; 386 default: 387 panic(); 388 } 389 } 390 391 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 392 { 393 uint32_t iwdg_cfg = 0U; 394 uint32_t otp_value; 395 396 #if defined(IMAGE_BL2) 397 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { 398 panic(); 399 } 400 #endif 401 402 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { 403 panic(); 404 } 405 406 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 407 iwdg_cfg |= IWDG_HW_ENABLED; 408 } 409 410 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 411 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 412 } 413 414 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 415 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 416 } 417 418 return iwdg_cfg; 419 } 420 421 #if defined(IMAGE_BL2) 422 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 423 { 424 uint32_t otp; 425 uint32_t result; 426 427 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { 428 panic(); 429 } 430 431 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { 432 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 433 } 434 435 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { 436 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 437 } 438 439 result = bsec_write_otp(otp, HW2_OTP); 440 if (result != BSEC_OK) { 441 return result; 442 } 443 444 /* Sticky lock OTP_IWDG (read and write) */ 445 if (!bsec_write_sr_lock(HW2_OTP, 1U) || 446 !bsec_write_sw_lock(HW2_OTP, 1U)) { 447 return BSEC_LOCK_FAIL; 448 } 449 450 return BSEC_OK; 451 } 452 #endif 453 454 /* Get the non-secure DDR size */ 455 uint32_t stm32mp_get_ddr_ns_size(void) 456 { 457 static uint32_t ddr_ns_size; 458 uint32_t ddr_size; 459 460 if (ddr_ns_size != 0U) { 461 return ddr_ns_size; 462 } 463 464 ddr_size = dt_get_ddr_size(); 465 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 466 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 467 panic(); 468 } 469 470 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 471 472 return ddr_ns_size; 473 } 474