1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/st/stm32_gpio.h> 10 #include <drivers/st/stm32_iwdg.h> 11 #include <libfdt.h> 12 #include <lib/xlat_tables/xlat_tables_v2.h> 13 14 #include <platform_def.h> 15 16 /* Internal layout of the 32bit OTP word board_id */ 17 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 18 #define BOARD_ID_BOARD_NB_SHIFT 16 19 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 20 #define BOARD_ID_VARCPN_SHIFT 12 21 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 22 #define BOARD_ID_REVISION_SHIFT 8 23 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 24 #define BOARD_ID_VARFG_SHIFT 4 25 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 26 27 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 28 BOARD_ID_BOARD_NB_SHIFT) 29 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 30 BOARD_ID_VARCPN_SHIFT) 31 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 32 BOARD_ID_REVISION_SHIFT) 33 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 34 BOARD_ID_VARFG_SHIFT) 35 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 36 37 #if defined(IMAGE_BL2) 38 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 39 STM32MP_SYSRAM_SIZE, \ 40 MT_MEMORY | \ 41 MT_RW | \ 42 MT_SECURE | \ 43 MT_EXECUTE_NEVER) 44 #elif defined(IMAGE_BL32) 45 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 46 STM32MP_SEC_SYSRAM_SIZE, \ 47 MT_MEMORY | \ 48 MT_RW | \ 49 MT_SECURE | \ 50 MT_EXECUTE_NEVER) 51 52 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 53 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 54 STM32MP_NS_SYSRAM_SIZE, \ 55 MT_DEVICE | \ 56 MT_RW | \ 57 MT_NS | \ 58 MT_EXECUTE_NEVER) 59 #endif 60 61 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 62 STM32MP1_DEVICE1_SIZE, \ 63 MT_DEVICE | \ 64 MT_RW | \ 65 MT_SECURE | \ 66 MT_EXECUTE_NEVER) 67 68 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 69 STM32MP1_DEVICE2_SIZE, \ 70 MT_DEVICE | \ 71 MT_RW | \ 72 MT_SECURE | \ 73 MT_EXECUTE_NEVER) 74 75 #if defined(IMAGE_BL2) 76 static const mmap_region_t stm32mp1_mmap[] = { 77 MAP_SEC_SYSRAM, 78 MAP_DEVICE1, 79 MAP_DEVICE2, 80 {0} 81 }; 82 #endif 83 #if defined(IMAGE_BL32) 84 static const mmap_region_t stm32mp1_mmap[] = { 85 MAP_SEC_SYSRAM, 86 MAP_NS_SYSRAM, 87 MAP_DEVICE1, 88 MAP_DEVICE2, 89 {0} 90 }; 91 #endif 92 93 void configure_mmu(void) 94 { 95 mmap_add(stm32mp1_mmap); 96 init_xlat_tables(); 97 98 enable_mmu_svc_mon(0); 99 } 100 101 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 102 { 103 if (bank == GPIO_BANK_Z) { 104 return GPIOZ_BASE; 105 } 106 107 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 108 109 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 110 } 111 112 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 113 { 114 if (bank == GPIO_BANK_Z) { 115 return 0; 116 } 117 118 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 119 120 return bank * GPIO_BANK_OFFSET; 121 } 122 123 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 124 { 125 if (bank == GPIO_BANK_Z) { 126 return true; 127 } 128 129 return false; 130 } 131 132 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 133 { 134 if (bank == GPIO_BANK_Z) { 135 return GPIOZ; 136 } 137 138 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 139 140 return GPIOA + (bank - GPIO_BANK_A); 141 } 142 143 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 144 { 145 switch (bank) { 146 case GPIO_BANK_A: 147 case GPIO_BANK_B: 148 case GPIO_BANK_C: 149 case GPIO_BANK_D: 150 case GPIO_BANK_E: 151 case GPIO_BANK_F: 152 case GPIO_BANK_G: 153 case GPIO_BANK_H: 154 case GPIO_BANK_I: 155 case GPIO_BANK_J: 156 case GPIO_BANK_K: 157 return fdt_path_offset(fdt, "/soc/pin-controller"); 158 case GPIO_BANK_Z: 159 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 160 default: 161 panic(); 162 } 163 } 164 165 #if STM32MP_UART_PROGRAMMER 166 /* 167 * UART Management 168 */ 169 static const uintptr_t stm32mp1_uart_addresses[8] = { 170 USART1_BASE, 171 USART2_BASE, 172 USART3_BASE, 173 UART4_BASE, 174 UART5_BASE, 175 USART6_BASE, 176 UART7_BASE, 177 UART8_BASE, 178 }; 179 180 uintptr_t get_uart_address(uint32_t instance_nb) 181 { 182 if ((instance_nb == 0U) || 183 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 184 return 0U; 185 } 186 187 return stm32mp1_uart_addresses[instance_nb - 1U]; 188 } 189 #endif 190 191 #if STM32MP_USB_PROGRAMMER 192 struct gpio_bank_pin_list { 193 uint32_t bank; 194 uint32_t pin; 195 }; 196 197 static const struct gpio_bank_pin_list gpio_list[] = { 198 { /* USART2_RX: GPIOA3 */ 199 .bank = 0U, 200 .pin = 3U, 201 }, 202 { /* USART3_RX: GPIOB12 */ 203 .bank = 1U, 204 .pin = 12U, 205 }, 206 { /* UART4_RX: GPIOB2 */ 207 .bank = 1U, 208 .pin = 2U, 209 }, 210 { /* UART5_RX: GPIOB4 */ 211 .bank = 1U, 212 .pin = 5U, 213 }, 214 { /* USART6_RX: GPIOC7 */ 215 .bank = 2U, 216 .pin = 7U, 217 }, 218 { /* UART7_RX: GPIOF6 */ 219 .bank = 5U, 220 .pin = 6U, 221 }, 222 { /* UART8_RX: GPIOE0 */ 223 .bank = 4U, 224 .pin = 0U, 225 }, 226 }; 227 228 void stm32mp1_deconfigure_uart_pins(void) 229 { 230 size_t i; 231 232 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 233 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 234 } 235 } 236 #endif 237 238 uint32_t stm32mp_get_chip_version(void) 239 { 240 uint32_t version = 0U; 241 242 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 243 INFO("Cannot get CPU version, debug disabled\n"); 244 return 0U; 245 } 246 247 return version; 248 } 249 250 uint32_t stm32mp_get_chip_dev_id(void) 251 { 252 uint32_t dev_id; 253 254 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 255 INFO("Use default chip ID, debug disabled\n"); 256 dev_id = STM32MP1_CHIP_ID; 257 } 258 259 return dev_id; 260 } 261 262 static uint32_t get_part_number(void) 263 { 264 static uint32_t part_number; 265 266 if (part_number != 0U) { 267 return part_number; 268 } 269 270 if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { 271 panic(); 272 } 273 274 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 275 PART_NUMBER_OTP_PART_SHIFT; 276 277 part_number |= stm32mp_get_chip_dev_id() << 16; 278 279 return part_number; 280 } 281 282 static uint32_t get_cpu_package(void) 283 { 284 uint32_t package; 285 286 if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { 287 panic(); 288 } 289 290 package = (package & PACKAGE_OTP_PKG_MASK) >> 291 PACKAGE_OTP_PKG_SHIFT; 292 293 return package; 294 } 295 296 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 297 { 298 char *cpu_s, *cpu_r, *pkg; 299 300 /* MPUs Part Numbers */ 301 switch (get_part_number()) { 302 case STM32MP157C_PART_NB: 303 cpu_s = "157C"; 304 break; 305 case STM32MP157A_PART_NB: 306 cpu_s = "157A"; 307 break; 308 case STM32MP153C_PART_NB: 309 cpu_s = "153C"; 310 break; 311 case STM32MP153A_PART_NB: 312 cpu_s = "153A"; 313 break; 314 case STM32MP151C_PART_NB: 315 cpu_s = "151C"; 316 break; 317 case STM32MP151A_PART_NB: 318 cpu_s = "151A"; 319 break; 320 case STM32MP157F_PART_NB: 321 cpu_s = "157F"; 322 break; 323 case STM32MP157D_PART_NB: 324 cpu_s = "157D"; 325 break; 326 case STM32MP153F_PART_NB: 327 cpu_s = "153F"; 328 break; 329 case STM32MP153D_PART_NB: 330 cpu_s = "153D"; 331 break; 332 case STM32MP151F_PART_NB: 333 cpu_s = "151F"; 334 break; 335 case STM32MP151D_PART_NB: 336 cpu_s = "151D"; 337 break; 338 default: 339 cpu_s = "????"; 340 break; 341 } 342 343 /* Package */ 344 switch (get_cpu_package()) { 345 case PKG_AA_LFBGA448: 346 pkg = "AA"; 347 break; 348 case PKG_AB_LFBGA354: 349 pkg = "AB"; 350 break; 351 case PKG_AC_TFBGA361: 352 pkg = "AC"; 353 break; 354 case PKG_AD_TFBGA257: 355 pkg = "AD"; 356 break; 357 default: 358 pkg = "??"; 359 break; 360 } 361 362 /* REVISION */ 363 switch (stm32mp_get_chip_version()) { 364 case STM32MP1_REV_B: 365 cpu_r = "B"; 366 break; 367 case STM32MP1_REV_Z: 368 cpu_r = "Z"; 369 break; 370 default: 371 cpu_r = "?"; 372 break; 373 } 374 375 snprintf(name, STM32_SOC_NAME_SIZE, 376 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 377 } 378 379 void stm32mp_print_cpuinfo(void) 380 { 381 char name[STM32_SOC_NAME_SIZE]; 382 383 stm32mp_get_soc_name(name); 384 NOTICE("CPU: %s\n", name); 385 } 386 387 void stm32mp_print_boardinfo(void) 388 { 389 uint32_t board_id; 390 uint32_t board_otp; 391 int bsec_node, bsec_board_id_node; 392 void *fdt; 393 const fdt32_t *cuint; 394 395 if (fdt_get_address(&fdt) == 0) { 396 panic(); 397 } 398 399 bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); 400 if (bsec_node < 0) { 401 return; 402 } 403 404 bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); 405 if (bsec_board_id_node <= 0) { 406 return; 407 } 408 409 cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); 410 if (cuint == NULL) { 411 panic(); 412 } 413 414 board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); 415 416 if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { 417 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 418 return; 419 } 420 421 if (board_id != 0U) { 422 char rev[2]; 423 424 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 425 rev[1] = '\0'; 426 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 427 BOARD_ID2NB(board_id), 428 BOARD_ID2VARCPN(board_id), 429 BOARD_ID2VARFG(board_id), 430 rev, 431 BOARD_ID2BOM(board_id)); 432 } 433 } 434 435 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 436 bool stm32mp_is_single_core(void) 437 { 438 switch (get_part_number()) { 439 case STM32MP151A_PART_NB: 440 case STM32MP151C_PART_NB: 441 case STM32MP151D_PART_NB: 442 case STM32MP151F_PART_NB: 443 return true; 444 default: 445 return false; 446 } 447 } 448 449 /* Return true when device is in closed state */ 450 bool stm32mp_is_closed_device(void) 451 { 452 uint32_t value; 453 454 if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || 455 (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { 456 return true; 457 } 458 459 return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; 460 } 461 462 uint32_t stm32_iwdg_get_instance(uintptr_t base) 463 { 464 switch (base) { 465 case IWDG1_BASE: 466 return IWDG1_INST; 467 case IWDG2_BASE: 468 return IWDG2_INST; 469 default: 470 panic(); 471 } 472 } 473 474 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 475 { 476 uint32_t iwdg_cfg = 0U; 477 uint32_t otp_value; 478 479 #if defined(IMAGE_BL2) 480 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { 481 panic(); 482 } 483 #endif 484 485 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { 486 panic(); 487 } 488 489 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 490 iwdg_cfg |= IWDG_HW_ENABLED; 491 } 492 493 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 494 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 495 } 496 497 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 498 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 499 } 500 501 return iwdg_cfg; 502 } 503 504 #if defined(IMAGE_BL2) 505 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 506 { 507 uint32_t otp; 508 uint32_t result; 509 510 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { 511 panic(); 512 } 513 514 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { 515 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 516 } 517 518 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { 519 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 520 } 521 522 result = bsec_write_otp(otp, HW2_OTP); 523 if (result != BSEC_OK) { 524 return result; 525 } 526 527 /* Sticky lock OTP_IWDG (read and write) */ 528 if (!bsec_write_sr_lock(HW2_OTP, 1U) || 529 !bsec_write_sw_lock(HW2_OTP, 1U)) { 530 return BSEC_LOCK_FAIL; 531 } 532 533 return BSEC_OK; 534 } 535 #endif 536 537 #if STM32MP_USE_STM32IMAGE 538 /* Get the non-secure DDR size */ 539 uint32_t stm32mp_get_ddr_ns_size(void) 540 { 541 static uint32_t ddr_ns_size; 542 uint32_t ddr_size; 543 544 if (ddr_ns_size != 0U) { 545 return ddr_ns_size; 546 } 547 548 ddr_size = dt_get_ddr_size(); 549 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 550 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 551 panic(); 552 } 553 554 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 555 556 return ddr_ns_size; 557 } 558 #endif /* STM32MP_USE_STM32IMAGE */ 559