1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <drivers/st/stm32_iwdg.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 16 /* Internal layout of the 32bit OTP word board_id */ 17 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 18 #define BOARD_ID_BOARD_NB_SHIFT 16 19 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 20 #define BOARD_ID_VARCPN_SHIFT 12 21 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 22 #define BOARD_ID_REVISION_SHIFT 8 23 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 24 #define BOARD_ID_VARFG_SHIFT 4 25 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 26 27 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 28 BOARD_ID_BOARD_NB_SHIFT) 29 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 30 BOARD_ID_VARCPN_SHIFT) 31 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 32 BOARD_ID_REVISION_SHIFT) 33 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 34 BOARD_ID_VARFG_SHIFT) 35 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 36 37 #if defined(IMAGE_BL2) 38 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 39 STM32MP_SYSRAM_SIZE, \ 40 MT_MEMORY | \ 41 MT_RW | \ 42 MT_SECURE | \ 43 MT_EXECUTE_NEVER) 44 #elif defined(IMAGE_BL32) 45 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 46 STM32MP_SEC_SYSRAM_SIZE, \ 47 MT_MEMORY | \ 48 MT_RW | \ 49 MT_SECURE | \ 50 MT_EXECUTE_NEVER) 51 52 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 53 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 54 STM32MP_NS_SYSRAM_SIZE, \ 55 MT_DEVICE | \ 56 MT_RW | \ 57 MT_NS | \ 58 MT_EXECUTE_NEVER) 59 #endif 60 61 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 62 STM32MP1_DEVICE1_SIZE, \ 63 MT_DEVICE | \ 64 MT_RW | \ 65 MT_SECURE | \ 66 MT_EXECUTE_NEVER) 67 68 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 69 STM32MP1_DEVICE2_SIZE, \ 70 MT_DEVICE | \ 71 MT_RW | \ 72 MT_SECURE | \ 73 MT_EXECUTE_NEVER) 74 75 #if defined(IMAGE_BL2) 76 static const mmap_region_t stm32mp1_mmap[] = { 77 MAP_SEC_SYSRAM, 78 MAP_DEVICE1, 79 MAP_DEVICE2, 80 {0} 81 }; 82 #endif 83 #if defined(IMAGE_BL32) 84 static const mmap_region_t stm32mp1_mmap[] = { 85 MAP_SEC_SYSRAM, 86 MAP_NS_SYSRAM, 87 MAP_DEVICE1, 88 MAP_DEVICE2, 89 {0} 90 }; 91 #endif 92 93 void configure_mmu(void) 94 { 95 mmap_add(stm32mp1_mmap); 96 init_xlat_tables(); 97 98 enable_mmu_svc_mon(0); 99 } 100 101 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 102 { 103 if (bank == GPIO_BANK_Z) { 104 return GPIOZ_BASE; 105 } 106 107 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 108 109 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 110 } 111 112 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 113 { 114 if (bank == GPIO_BANK_Z) { 115 return 0; 116 } 117 118 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 119 120 return bank * GPIO_BANK_OFFSET; 121 } 122 123 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 124 { 125 if (bank == GPIO_BANK_Z) { 126 return GPIOZ; 127 } 128 129 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 130 131 return GPIOA + (bank - GPIO_BANK_A); 132 } 133 134 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 135 { 136 switch (bank) { 137 case GPIO_BANK_A: 138 case GPIO_BANK_B: 139 case GPIO_BANK_C: 140 case GPIO_BANK_D: 141 case GPIO_BANK_E: 142 case GPIO_BANK_F: 143 case GPIO_BANK_G: 144 case GPIO_BANK_H: 145 case GPIO_BANK_I: 146 case GPIO_BANK_J: 147 case GPIO_BANK_K: 148 return fdt_path_offset(fdt, "/soc/pin-controller"); 149 case GPIO_BANK_Z: 150 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 151 default: 152 panic(); 153 } 154 } 155 156 #if STM32MP_UART_PROGRAMMER 157 /* 158 * UART Management 159 */ 160 static const uintptr_t stm32mp1_uart_addresses[8] = { 161 USART1_BASE, 162 USART2_BASE, 163 USART3_BASE, 164 UART4_BASE, 165 UART5_BASE, 166 USART6_BASE, 167 UART7_BASE, 168 UART8_BASE, 169 }; 170 171 uintptr_t get_uart_address(uint32_t instance_nb) 172 { 173 if ((instance_nb == 0U) || 174 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 175 return 0U; 176 } 177 178 return stm32mp1_uart_addresses[instance_nb - 1U]; 179 } 180 #endif 181 182 uint32_t stm32mp_get_chip_version(void) 183 { 184 uint32_t version = 0U; 185 186 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 187 INFO("Cannot get CPU version, debug disabled\n"); 188 return 0U; 189 } 190 191 return version; 192 } 193 194 uint32_t stm32mp_get_chip_dev_id(void) 195 { 196 uint32_t dev_id; 197 198 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 199 INFO("Use default chip ID, debug disabled\n"); 200 dev_id = STM32MP1_CHIP_ID; 201 } 202 203 return dev_id; 204 } 205 206 static uint32_t get_part_number(void) 207 { 208 static uint32_t part_number; 209 210 if (part_number != 0U) { 211 return part_number; 212 } 213 214 if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { 215 panic(); 216 } 217 218 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 219 PART_NUMBER_OTP_PART_SHIFT; 220 221 part_number |= stm32mp_get_chip_dev_id() << 16; 222 223 return part_number; 224 } 225 226 static uint32_t get_cpu_package(void) 227 { 228 uint32_t package; 229 230 if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { 231 panic(); 232 } 233 234 package = (package & PACKAGE_OTP_PKG_MASK) >> 235 PACKAGE_OTP_PKG_SHIFT; 236 237 return package; 238 } 239 240 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 241 { 242 char *cpu_s, *cpu_r, *pkg; 243 244 /* MPUs Part Numbers */ 245 switch (get_part_number()) { 246 case STM32MP157C_PART_NB: 247 cpu_s = "157C"; 248 break; 249 case STM32MP157A_PART_NB: 250 cpu_s = "157A"; 251 break; 252 case STM32MP153C_PART_NB: 253 cpu_s = "153C"; 254 break; 255 case STM32MP153A_PART_NB: 256 cpu_s = "153A"; 257 break; 258 case STM32MP151C_PART_NB: 259 cpu_s = "151C"; 260 break; 261 case STM32MP151A_PART_NB: 262 cpu_s = "151A"; 263 break; 264 case STM32MP157F_PART_NB: 265 cpu_s = "157F"; 266 break; 267 case STM32MP157D_PART_NB: 268 cpu_s = "157D"; 269 break; 270 case STM32MP153F_PART_NB: 271 cpu_s = "153F"; 272 break; 273 case STM32MP153D_PART_NB: 274 cpu_s = "153D"; 275 break; 276 case STM32MP151F_PART_NB: 277 cpu_s = "151F"; 278 break; 279 case STM32MP151D_PART_NB: 280 cpu_s = "151D"; 281 break; 282 default: 283 cpu_s = "????"; 284 break; 285 } 286 287 /* Package */ 288 switch (get_cpu_package()) { 289 case PKG_AA_LFBGA448: 290 pkg = "AA"; 291 break; 292 case PKG_AB_LFBGA354: 293 pkg = "AB"; 294 break; 295 case PKG_AC_TFBGA361: 296 pkg = "AC"; 297 break; 298 case PKG_AD_TFBGA257: 299 pkg = "AD"; 300 break; 301 default: 302 pkg = "??"; 303 break; 304 } 305 306 /* REVISION */ 307 switch (stm32mp_get_chip_version()) { 308 case STM32MP1_REV_B: 309 cpu_r = "B"; 310 break; 311 case STM32MP1_REV_Z: 312 cpu_r = "Z"; 313 break; 314 default: 315 cpu_r = "?"; 316 break; 317 } 318 319 snprintf(name, STM32_SOC_NAME_SIZE, 320 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 321 } 322 323 void stm32mp_print_cpuinfo(void) 324 { 325 char name[STM32_SOC_NAME_SIZE]; 326 327 stm32mp_get_soc_name(name); 328 NOTICE("CPU: %s\n", name); 329 } 330 331 void stm32mp_print_boardinfo(void) 332 { 333 uint32_t board_id; 334 uint32_t board_otp; 335 int bsec_node, bsec_board_id_node; 336 void *fdt; 337 const fdt32_t *cuint; 338 339 if (fdt_get_address(&fdt) == 0) { 340 panic(); 341 } 342 343 bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); 344 if (bsec_node < 0) { 345 return; 346 } 347 348 bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); 349 if (bsec_board_id_node <= 0) { 350 return; 351 } 352 353 cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); 354 if (cuint == NULL) { 355 panic(); 356 } 357 358 board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); 359 360 if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { 361 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 362 return; 363 } 364 365 if (board_id != 0U) { 366 char rev[2]; 367 368 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 369 rev[1] = '\0'; 370 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 371 BOARD_ID2NB(board_id), 372 BOARD_ID2VARCPN(board_id), 373 BOARD_ID2VARFG(board_id), 374 rev, 375 BOARD_ID2BOM(board_id)); 376 } 377 } 378 379 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 380 bool stm32mp_is_single_core(void) 381 { 382 switch (get_part_number()) { 383 case STM32MP151A_PART_NB: 384 case STM32MP151C_PART_NB: 385 case STM32MP151D_PART_NB: 386 case STM32MP151F_PART_NB: 387 return true; 388 default: 389 return false; 390 } 391 } 392 393 /* Return true when device is in closed state */ 394 bool stm32mp_is_closed_device(void) 395 { 396 uint32_t value; 397 398 if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || 399 (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { 400 return true; 401 } 402 403 return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; 404 } 405 406 uint32_t stm32_iwdg_get_instance(uintptr_t base) 407 { 408 switch (base) { 409 case IWDG1_BASE: 410 return IWDG1_INST; 411 case IWDG2_BASE: 412 return IWDG2_INST; 413 default: 414 panic(); 415 } 416 } 417 418 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 419 { 420 uint32_t iwdg_cfg = 0U; 421 uint32_t otp_value; 422 423 #if defined(IMAGE_BL2) 424 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { 425 panic(); 426 } 427 #endif 428 429 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { 430 panic(); 431 } 432 433 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 434 iwdg_cfg |= IWDG_HW_ENABLED; 435 } 436 437 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 438 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 439 } 440 441 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 442 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 443 } 444 445 return iwdg_cfg; 446 } 447 448 #if defined(IMAGE_BL2) 449 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 450 { 451 uint32_t otp; 452 uint32_t result; 453 454 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { 455 panic(); 456 } 457 458 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { 459 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 460 } 461 462 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { 463 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 464 } 465 466 result = bsec_write_otp(otp, HW2_OTP); 467 if (result != BSEC_OK) { 468 return result; 469 } 470 471 /* Sticky lock OTP_IWDG (read and write) */ 472 if (!bsec_write_sr_lock(HW2_OTP, 1U) || 473 !bsec_write_sw_lock(HW2_OTP, 1U)) { 474 return BSEC_LOCK_FAIL; 475 } 476 477 return BSEC_OK; 478 } 479 #endif 480 481 #if STM32MP_USE_STM32IMAGE 482 /* Get the non-secure DDR size */ 483 uint32_t stm32mp_get_ddr_ns_size(void) 484 { 485 static uint32_t ddr_ns_size; 486 uint32_t ddr_size; 487 488 if (ddr_ns_size != 0U) { 489 return ddr_ns_size; 490 } 491 492 ddr_size = dt_get_ddr_size(); 493 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 494 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 495 panic(); 496 } 497 498 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 499 500 return ddr_ns_size; 501 } 502 #endif /* STM32MP_USE_STM32IMAGE */ 503