refactor(st): use %c to display board info

Now that %c is supported in log functions, use it instead of creating a
temporary string in stm32_display_board_info(). This also saves a few
bytes of code

refactor(st): use %c to display board info

Now that %c is supported in log functions, use it instead of creating a
temporary string in stm32_display_board_info(). This also saves a few
bytes of code.

Change-Id: If071ed83b92bd30aec425f5b33f66f87c066dae5
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(stm32mp2): remove unused macro PLAT_NB_GPIO_REGUS

The macro PLAT_NB_GPIO_REGUS is not used, remove it.

Change-Id: I4303545ee92be95cd7040a20dfe79d417dc07be4
Signed-off-by: Yann Gautier <yann.gau

fix(stm32mp2): remove unused macro PLAT_NB_GPIO_REGUS

The macro PLAT_NB_GPIO_REGUS is not used, remove it.

Change-Id: I4303545ee92be95cd7040a20dfe79d417dc07be4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "fix(stm32mp2): correct ORR instruction in plat_crash_console_init" into integration

Merge "fix(st): restore support for multiple entries in DTB_FILE_NAME" into integration

fix(stm32mp2): correct ORR instruction in plat_crash_console_init

For some cases, the value (DEBUG_UART_TX_GPIO_ALTERNATE <<
((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) cannot fit the
p

fix(stm32mp2): correct ORR instruction in plat_crash_console_init

For some cases, the value (DEBUG_UART_TX_GPIO_ALTERNATE <<
((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) cannot fit the
pattern for immediate value for ORR instruction.
Use a temporary register, filled with mov_imm macro.
While at it change the other ORR or BIC instructions that could have the
same issue.

Change-Id: If4434b910463af7d55b9e4ea6562a67e606b02bb
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(st): restore support for multiple entries in DTB_FILE_NAME

Commit e772a6d1864a ("stm32mp1: platform.mk: support generating multiple
images in one build") allowed DTB_FILE_NAME to contain multipl

fix(st): restore support for multiple entries in DTB_FILE_NAME

Commit e772a6d1864a ("stm32mp1: platform.mk: support generating multiple
images in one build") allowed DTB_FILE_NAME to contain multiple entries,
thereby allowing to build all the executable code once and then link it
against each device tree one by one.

This makes for easier build system integration as one recipe/package can
generate multiple images at once.

This was broken by below mentioned commit, because it assumed
DTB_FILE_NAME to contain only a single entry. Rework the -sp_min suffix
logic to fix this regression.

Fixes: 71ba1647e09c ("feat(st): use dedicated version of DT for SP_MIN")
Change-Id: Ib596a404ccda92c3a3c29e276930a74f147734fc
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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feat(stm32mp2): add a new stm32mp21 power compatible

Introduce new compatible st,stm32mp21-pwr. It is based st,stm32mp25-pwr but
without vddio4.

Signed-off-by: Valentin Caron <valentin.caron@foss.s

feat(stm32mp2): add a new stm32mp21 power compatible

Introduce new compatible st,stm32mp21-pwr. It is based st,stm32mp25-pwr but
without vddio4.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ibf22bec75aa310eb0f3d1e1f3fc603498f9e49b8

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feat(stm32mp2): add RIFSC USB configuration for variants

Add RIFSC related service call for STM32MP21 and STM32MP23 variants
with dedicated parameters. Add definitions for STM32MP21 because USB OTG

feat(stm32mp2): add RIFSC USB configuration for variants

Add RIFSC related service call for STM32MP21 and STM32MP23 variants
with dedicated parameters. Add definitions for STM32MP21 because USB OTG
Add USB OTG_HS definitions for STM32MP21.

Change-Id: I5276192ed257c3461bf7d84f0900c30fc4ad60ae
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp2): include dedicated RIFSC ID headers

RIFSC IDs differs from each STM32MP2 variants.
Include the correct files depending on the SoC that is compiled.

Signed-off-by: Nicolas Le Bayon <n

feat(stm32mp2): include dedicated RIFSC ID headers

RIFSC IDs differs from each STM32MP2 variants.
Include the correct files depending on the SoC that is compiled.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I26d6119e0b5be0c113111b4781ab39567d19c1fb

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feat(stm32mp21): enable USBOTG DFU

USBOTG DFU is present on STM32MP21. Enable related driver and adapt
platform init sequence.

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Nicolas L

feat(stm32mp21): enable USBOTG DFU

USBOTG DFU is present on STM32MP21. Enable related driver and adapt
platform init sequence.

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ia7d885c86400b7f90bd605bd797612007989b909

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feat(stm32mp2): manage RISAF MCE key for STM32MP21

On STM32MP21, RISAF encryption key is automatically generated from the
HWKEY (derivation) using RNG2 IP and enabled by a dummy write sequence
on RI

feat(stm32mp2): manage RISAF MCE key for STM32MP21

On STM32MP21, RISAF encryption key is automatically generated from the
HWKEY (derivation) using RNG2 IP and enabled by a dummy write sequence
on RISAF encryption key registers.
The context seed saving can then be replaced by new MCE one.
Set maximum size at platform level.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3f1571eaff1749758c7ed3d7522d629f8a7eb865

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feat(stm32mp2): define UART8 and UART9 under STM32MP25 flag

On STM32MP21 and STM32MP23, there are no UART8 and UART9.
The STM32MP_NB_OF_UART is then 7.
The stm32mp2_uart_addresses[] struct is also u

feat(stm32mp2): define UART8 and UART9 under STM32MP25 flag

On STM32MP21 and STM32MP23, there are no UART8 and UART9.
The STM32MP_NB_OF_UART is then 7.
The stm32mp2_uart_addresses[] struct is also updated.

Change-Id: I2019210207d9c3f24e2f29af67ad53ea54f8acff
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp21): display package type

The package type is read from OTP fuse. Display it with other SoC
information at boot.

Change-Id: Ib75461f4eebd56be5e29c93d488c0a8f84d5575a
Signed-off-by: Yann

feat(stm32mp21): display package type

The package type is read from OTP fuse. Display it with other SoC
information at boot.

Change-Id: Ib75461f4eebd56be5e29c93d488c0a8f84d5575a
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp21): add SoC part numbers

Add STM32MP21xx SoCs part numbers and the code to display it at boot.
STM32MP21x is always single core, directly return true in function
stm32mp_is_single_core(

feat(stm32mp21): add SoC part numbers

Add STM32MP21xx SoCs part numbers and the code to display it at boot.
STM32MP21x is always single core, directly return true in function
stm32mp_is_single_core().
As for STM32MP25, STM32MP21xC and STM32MP21xF can support
authenticated boot.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I586b584a3dab61ea9507a2c798a02ebdc9de0052

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feat(stm32mp21): update boot API header version

Update BOOT_API_HEADER_VERSION to header version 2.3 for STM32MP21.

STM32MP21 can use sha384 or sha256 as hash algorithm.

Set sha256 as hash algorit

feat(stm32mp21): update boot API header version

Update BOOT_API_HEADER_VERSION to header version 2.3 for STM32MP21.

STM32MP21 can use sha384 or sha256 as hash algorithm.

Set sha256 as hash algorithm by default. Sha384 support must be
developed.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: If76f1f15752ab12b0897003ffef6bfcab275c00d

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feat(stm32mp21): update STM32 header size for STM32MP21

On STM32MP21, the STM32 header v2.3 is used, and the length is 576
bytes, versus 512 bytes for all other STM32MP2 variants.

Signed-off-by: Ni

feat(stm32mp21): update STM32 header size for STM32MP21

On STM32MP21, the STM32 header v2.3 is used, and the length is 576
bytes, versus 512 bytes for all other STM32MP2 variants.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I8a5778ac8f6331ec083f122150231ede245be514

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feat(stm32mp21): remove GPIOJ and GPIOK

On STM32MP21, there are no GPIOJ and GPIOK instance.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I53d40691e4d084166c5d13c6475a6e821c

feat(stm32mp21): remove GPIOJ and GPIOK

On STM32MP21, there are no GPIOJ and GPIOK instance.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I53d40691e4d084166c5d13c6475a6e821c8d9256

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feat(stm32mp21): update SRAM1 and RETRAM base address

On STM32MP21, SRAM1 is located in range 0x0E060000-0x0E06FFFF.
RETRAM range is 0x0E040000-0x0E05FFFF.

Signed-off-by: Yann Gautier <yann.gautier

feat(stm32mp21): update SRAM1 and RETRAM base address

On STM32MP21, SRAM1 is located in range 0x0E060000-0x0E06FFFF.
RETRAM range is 0x0E040000-0x0E05FFFF.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I0ac34a1efefa601207eb8e66d66f7b41c37a5441

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feat(stm32mp21): manage STM32MP21 DT overlays

Add BL2 and BL31 DT overlays for STM32MP21 and their management in
platform.mk file.

Change-Id: I6ea0861280befa6b4f20c7cd7feef97cbdb7a0ab
Signed-off-by

feat(stm32mp21): manage STM32MP21 DT overlays

Add BL2 and BL31 DT overlays for STM32MP21 and their management in
platform.mk file.

Change-Id: I6ea0861280befa6b4f20c7cd7feef97cbdb7a0ab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp23): manage STM32MP23 DT overlays

Add BL2 and BL31 DT overlays for STM32MP23 and their management in
platform.mk file.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-I

feat(stm32mp23): manage STM32MP23 DT overlays

Add BL2 and BL31 DT overlays for STM32MP23 and their management in
platform.mk file.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I1808f88f7959b9ee109769dba4b3d3148ec3b38b

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feat(stm32mp23): display package type

The package type is read from OTP fuse. Display it with other SoC
information at boot.

Change-Id: I855bd1ac8d96ca88a7e4ee5ac8b6f65697214cc9
Signed-off-by: Yann

feat(stm32mp23): display package type

The package type is read from OTP fuse. Display it with other SoC
information at boot.

Change-Id: I855bd1ac8d96ca88a7e4ee5ac8b6f65697214cc9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp23): add SoC part numbers

Add STM32MP23xx SoCs part numbers and the code to display it at boot.
As for STM32MP25, STM32MP23xC and STM32MP23xF can support
authenticated boot.

Signed-off-

feat(stm32mp23): add SoC part numbers

Add STM32MP23xx SoCs part numbers and the code to display it at boot.
As for STM32MP25, STM32MP23xC and STM32MP23xF can support
authenticated boot.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I9fd5cefa7df47ebb0263959a3180f5bfceb1c0dd

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feat(stm32mp1): make stpmic2 usable for STM32MP1

Update STPMIC2 driver to use it on STM32MP1 especially
STM32MP_STPMIC1L.

Change-Id: I0db727a093a6a85dca7a74be280c0d1af0e54417
Signed-off-by: Pascal

feat(stm32mp1): make stpmic2 usable for STM32MP1

Update STPMIC2 driver to use it on STM32MP1 especially
STM32MP_STPMIC1L.

Change-Id: I0db727a093a6a85dca7a74be280c0d1af0e54417
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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fix(stm32mp2): reorder DDR3 and DDR4 power supply sequences

DDR power supply sequence has to respect the order described in the
specification.
Expected DDR3 order must be VREF / VTT / VDD.
Expected

fix(stm32mp2): reorder DDR3 and DDR4 power supply sequences

DDR power supply sequence has to respect the order described in the
specification.
Expected DDR3 order must be VREF / VTT / VDD.
Expected DDR4 order must be VPP / VREF / VTT / VDD.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I4dad32aad9f96f68d8c5e38a90c31c21badec1c2

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feat(stm32mp1): rework ddr supplies handling

Retrieve DDR power supplies from the device-tree.
This patch requests to describe the DDR power supplies
in the DT_DDR_COMPAT node.
This patch assumes al

feat(stm32mp1): rework ddr supplies handling

Retrieve DDR power supplies from the device-tree.
This patch requests to describe the DDR power supplies
in the DT_DDR_COMPAT node.
This patch assumes also that the sink-source or
the bypass property was set in the device-tree in the ldo3
node.

Change-Id: Ida9dd705b623a8bd40dd206cc08e2d550446b172
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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