feat(stm32mp2): add RIFSC/RISAB protection for USB3DR

Add RIFSC/RISAB protection for USB3-IP:
- USB3DR Peripheral only accessible form Secure/Priv
- USB3DR Master is Secure/Priv to access SYSRAM in

feat(stm32mp2): add RIFSC/RISAB protection for USB3DR

Add RIFSC/RISAB protection for USB3-IP:
- USB3DR Peripheral only accessible form Secure/Priv
- USB3DR Master is Secure/Priv to access SYSRAM in bl2 plat setup.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Change-Id: Ic735cd1cadc5a3a52065b0c7db328268d405a77c

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feat(st-drivers): add RIFSC driver

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave periph

feat(st-drivers): add RIFSC driver

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.

This doesn't support semaphore acquisition.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iba4cdbf53243292fa0b42cad8392c43734dd9bc2

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feat(stm32mp2): add STM32MP_USB_PROGRAMMER support

Add STM32MP_USB_PROGRAMMER support for STM32MP2 platform by
compiling usb-dwc3 driver and adding the requested memory and
USB-DFU configurations.

feat(stm32mp2): add STM32MP_USB_PROGRAMMER support

Add STM32MP_USB_PROGRAMMER support for STM32MP2 platform by
compiling usb-dwc3 driver and adding the requested memory and
USB-DFU configurations.

The DFU stack is used in BL2 when STM32MP_USB_PROGRAMMER is activated
by the STMicroelectronics tools STM32Cubeprogrammer for serial boot mode
on USB.

Change-Id: I0dd74152ee6e0a3a3d1332d4fb2edbae7743fcc1
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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feat(stm32mp2): generate FIP for DDR initialization

Generate a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

It is loaded in internal memory

feat(stm32mp2): generate FIP for DDR initialization

Generate a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

It is loaded in internal memory before to be used with support of
the FIP memmap.

To ease Trusted Boot porting for serial boot, we can use TOOL_ADD_IMG
with a DDR_ prefix. To avoid the overriding rule issue with the check
rule in TOOL_ADD_IMG, a copy of the STM32MP_DDR_FW variable is created.

Change-Id: I3a051ca2b258771e48c6e9fed9d77ab512c2416f
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(stm32mp2): add support for minimal FIP with only DDR FW

Load a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

This DDR FIP is loaded at t

feat(stm32mp2): add support for minimal FIP with only DDR FW

Load a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.

This DDR FIP is loaded at the beginning of SYSRAM and used with
support of memmap features.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie413233de0e4d785b2d669087da34110df557ad3

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fix(st): allow several call of stm32cubeprog_uart_load

Update the function stm32cubeprog_uart_load() to skip the UART
initialization when the function is called a second time.

On STM32MP25, this fu

fix(st): allow several call of stm32cubeprog_uart_load

Update the function stm32cubeprog_uart_load() to skip the UART
initialization when the function is called a second time.

On STM32MP25, this function is called 2 times, first to load FIP DDR
in small internal memory and after DDR initialization, to load FIP in
this large external memory

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ibbb4ad44b89730d6c6101c89e56c59978d38cfed

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feat(st): update stm32cubeprogrammer API

Update the API stm32cubeprog_[uart/usb]_load() to provide the requested
phase; the phase is no more assumed to PHASE_SSBL.

Signed-off-by: Patrick Delaunay <

feat(st): update stm32cubeprogrammer API

Update the API stm32cubeprog_[uart/usb]_load() to provide the requested
phase; the phase is no more assumed to PHASE_SSBL.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3e14ce0bd5bfce59f141d672b0d66be04012820f

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feat(stm32mp1): add stm32_get_uid_otp

Add a generic function to get the unique device id (UID)
from the OTP.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id15dbb6668b4b

feat(stm32mp1): add stm32_get_uid_otp

Add a generic function to get the unique device id (UID)
from the OTP.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id15dbb6668b4bafe44e86c33e76ec64a3c982387

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fix(st): replace down counter by a timeout upon dfu detach

On stm32mp2, DFU detach sometimes makes subsequent usb start to fail.
The core doesn't have the time to properly finalize the last setup
ph

fix(st): replace down counter by a timeout upon dfu detach

On stm32mp2, DFU detach sometimes makes subsequent usb start to fail.
The core doesn't have the time to properly finalize the last setup
phase. This results in error logs seen:
ERROR: dwc3_handle_dev_event: 1688
ERROR: dwc3_handle_dev_event: 1692

Just enabling "DFU USB STOP" message hides the issue, sequentially:
usb_core_start()
...
usb_dfu_loop() // runs until DFU_DETACH command
--> while(it_count != 0U) {
usb_core_handle_it()
if (usb_dfu_detach_req)
it_count--; // down count from 100 to 0
}
...
INFO("DFU USB STOP...\n");
usb_core_stop()

The down-counter (it_count) value doesn't seem to be enough, and seems
not robust against CPU speed. So rather adopt a 100us timeout. It's
determined experimentally (above issue seems to be triggered around
20us to 30us, so keep some margin).

Change-Id: Iac37c346ad938cd917dfbd7e4622546d29ee7517
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>

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fix(st): add build directory for stm32image

Since patch to prevent build races on the build directory [1], there
could be issues to build stm32image tool, with parallel build, and when
using a custo

fix(st): add build directory for stm32image

Since patch to prevent build races on the build directory [1], there
could be issues to build stm32image tool, with parallel build, and when
using a custom BUILD_PLAT directory. Fix that the same way the other
tools were fixed (with: | $$(@D)/).

[1]: 774fb3798e43 fix(build): prevent races on the build directory

Change-Id: Idd3a43d2565018ea8755df69e7385f07fda7941f
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when t

fix: remove unused cpu_data related macros

There are no uses for CPU_DATA_PSCI_LOCK_OFFSET so it is removed.

PLAT_PCPU_DATA_SIZE is also unused in ST platforms and causes offsets
to mismatch when the linker garbage collects it. It is also removed.

CPU_DATA_PLAT_PCPU_OFFSET is also removed as its only use is in
rcar_lock_get() and related macros which are never called since all
calls of these macros lack an argument.

Change-Id: I883ab58c56b4082e0e8b19a8d8f6186945bcc58e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(stm32mp2): prepare DDR secure area encryption

The RISAF4 defines the DDR secure areas with specific security setup
(encryption). Its master key needs to be written before any activation.
This i

feat(stm32mp2): prepare DDR secure area encryption

The RISAF4 defines the DDR secure areas with specific security setup
(encryption). Its master key needs to be written before any activation.
This is done only if SoC supports encryption.

Change-Id: I38e6af65cadf9678a75be1b861ee0c5beea5bcb9
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(stm32mp2): add some platform helpers

Update STM32MP2 the platform files.
Implement the helpers for STM32MP2, as we have them for STM32MP1:
stm32mp_is_single_core, stm32mp_check_closed_device an

feat(stm32mp2): add some platform helpers

Update STM32MP2 the platform files.
Implement the helpers for STM32MP2, as we have them for STM32MP1:
stm32mp_is_single_core, stm32mp_check_closed_device and
stm32mp_is_auth_supported

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1554efdb05338f07b292e77175db5a564cc25c78

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feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.

The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2

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feat(stm32mp1): prepare DDR secure area encryption for STM32MP13

The Memory Cipher Engine (MCE) defines the DDR secure area with
specific security setup (encryption).
Its master key is randomly gene

feat(stm32mp1): prepare DDR secure area encryption for STM32MP13

The Memory Cipher Engine (MCE) defines the DDR secure area with
specific security setup (encryption).
Its master key is randomly generated (using RNG driver).
Initialize and configure MCE IP on platform side only if
authentication is supported at SoC level.

Change-Id: I034f45b0fd547d924cbc92c42298e1f3b1e7343c
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp1): enable MCE driver for STM32MP13

Enabled as BL2 sources.
Add MCE base address and key size in platform definitions.

Change-Id: Icb7d9d7a56806a86e6d0a76640a375a5b5e88a2a
Signed-off-by

feat(stm32mp1): enable MCE driver for STM32MP13

Enabled as BL2 sources.
Add MCE base address and key size in platform definitions.

Change-Id: Icb7d9d7a56806a86e6d0a76640a375a5b5e88a2a
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(st): add RNG minor version

Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608

feat(st): add RNG minor version

Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608bd5cad77616bf0c031c66a8312b65d3e68c5

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feat(stm32mp2): add HASH and RNG compilation

Add the drivers compilation in STM32MP2 platform.mk.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892

feat(stm32mp2): add HASH and RNG compilation

Add the drivers compilation in STM32MP2 platform.mk.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892eff66c99

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feat(st): use and override default MBedTLS config

Each time MbedTLS is updated, the default config may be updated. As
STM32MP platforms have their own config file, this needs to be aligned.
To avoid

feat(st): use and override default MBedTLS config

Each time MbedTLS is updated, the default config may be updated. As
STM32MP platforms have their own config file, this needs to be aligned.
To avoid this alignment, directly include the default config and
override some values for ST platforms, mainly heap size.
MBEDTLS_MPI_WINDOW_SIZE is also kept to avoid behavior change.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6a9c3141451ab7b11906a7139549d31cfff0581a

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feat(st): put stm32image tool in build directory

Following the series moving common tools compilation to the build
directory[1], do the same for stm32image tool.

[1]: cbd6cec3c3 feat(build): put fi

feat(st): put stm32image tool in build directory

Following the series moving common tools compilation to the build
directory[1], do the same for stm32image tool.

[1]: cbd6cec3c3 feat(build): put fiptool in the build directory

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If33556e98c4788350a29c8ad96dc574584b67abd

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feat(build): put crttool in the build directory

Same as fiptool. Move all artefacts to the platform build directory and
convert to the standard build macro to make things more generic. Leave
a symli

feat(build): put crttool in the build directory

Same as fiptool. Move all artefacts to the platform build directory and
convert to the standard build macro to make things more generic. Leave
a symlink for the final binary in case someone depends on it.

Change-Id: I82ef846a95474ba385377032fb185e548827bf5c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration

* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(s

Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration

* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(st): update stm32 linker scripts
fix(st): mark INCBIN-generated sections as SHF_ALLOC
feat(st): remove unsupported option for clang

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Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family

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feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32

feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32MP21,
STM32MP23 and STM32MP25 flags.
STM32MP23 will use the same RCC clock compatible of STM32MP25 SoC.

Change-Id: I6422cd0553067dc92f80da1ad8ec78cadf2432bb
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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refactor(stm32mp2): update display of reset reason

Update the check of reset reason management, update displayed string
aligned with reference manual (por_rstn/bor_rstn/Pin reset), add some
missing

refactor(stm32mp2): update display of reset reason

Update the check of reset reason management, update displayed string
aligned with reference manual (por_rstn/bor_rstn/Pin reset), add some
missing reset reason (C1RST) and reuse string to reduce the size of BL2.

Change-Id: I343a46d69bf0447cafed684eab1b2e812e08ab3a
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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