fix(build): ensure `$(ROT_KEY)` depends on correct directory rules

In order for directories to be automatically created when used as a
dependency, they must end with a forward slash (`/`). This is b

fix(build): ensure `$(ROT_KEY)` depends on correct directory rules

In order for directories to be automatically created when used as a
dependency, they must end with a forward slash (`/`). This is because we
have a pattern rule (`%/`) to create a directory anywhere where a
directory is required as a direct dependency.

Change-Id: Ib632d59da0745f6cadb0a839a62360aeca25c178
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(qemu): update rmmd_attest_get_platform_token()" into integration

fix(qemu): update rmmd_attest_get_platform_token()

Update the parameters to rmmd_attest_get_platform_token(), which can now
handle platform tokens larger than 4kB. Since the QEMU sample token is
sma

fix(qemu): update rmmd_attest_get_platform_token()

Update the parameters to rmmd_attest_get_platform_token(), which can now
handle platform tokens larger than 4kB. Since the QEMU sample token is
smaller than 4kB, our implementation remains the same. Take the
opportunity to clean up the function slightly.

Change-Id: Id5a1d576968ebd160d2b79c1f38392d4ecc89421
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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refactor(qemu): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-c

refactor(qemu): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cca-token-00.

This change replaces the static CCA platform token in QEMU.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/30812
[2] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/31036

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9153df1e6c1be81e669d5495dbe8d1a52e86cdff

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Merge changes If374b491,I6b63b9c6 into integration

* changes:
fix(qemu): exclude GPT reserve from BL32_MEM_SIZE
fix(qemu): fix L0 GPT page table mapping

chore(qemu): remove duplicate define

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: Id18abe80ab56fd51a9c2c1206b22d87f1e3871eb

fix(qemu): exclude GPT reserve from BL32_MEM_SIZE

BL32_MEM_SIZE fails to take into account the space reserved for L0 and
L1 GPTs at the end of secure DRAM, when ENABLE_RME==1.

Fixes: cd75693f5ed3 (

fix(qemu): exclude GPT reserve from BL32_MEM_SIZE

BL32_MEM_SIZE fails to take into account the space reserved for L0 and
L1 GPTs at the end of secure DRAM, when ENABLE_RME==1.

Fixes: cd75693f5ed3 ("feat(qemu): setup memory map for RME")
Change-Id: If374b491d82be93c195cf501a9d12b9965d85182
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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fix(qemu): fix L0 GPT page table mapping

Page table mappings are missing the bitlock pages introduced by commit
e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock"). Add them to
the L0 mapping

fix(qemu): fix L0 GPT page table mapping

Page table mappings are missing the bitlock pages introduced by commit
e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock"). Add them to
the L0 mapping.

Change-Id: I6b63b9c6ea4bf01ab1fac98723340272babe7bf8
Reported-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Fixes: e9bcbd7b2ee4 ("fix(qemu): allocate space for GPT bitlock")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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Merge "feat(handoff): fix register convention r1/x1 value on transfer list" into integration

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was chang

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).

As updating of TL's signature, register value of x1/r1 should be:

In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).

Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.

This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.

2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.

This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).

Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705

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Merge "fix(qemu): remove validate_ns_entrypoint" into integration

Merge "fix(qemu): allocate space for GPT bitlock" into integration

refactor(qemu-sbsa): use fdt_read_uint32_default more

We have fdt_read_uint32_default() function which allows us to use less
temporary variables. Let make use of it where applicable.

Signed-off-by:

refactor(qemu-sbsa): use fdt_read_uint32_default more

We have fdt_read_uint32_default() function which allows us to use less
temporary variables. Let make use of it where applicable.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I6fc8a87d5aac427703fd3c8b689e153ed58fa8b7

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feat(qemu-sbsa): handle the information of CPU topology

We add the support for adding cpus/topology to device tree in sbsaQemu
platform, and we can get this information via SMC calls:

- counting th

feat(qemu-sbsa): handle the information of CPU topology

We add the support for adding cpus/topology to device tree in sbsaQemu
platform, and we can get this information via SMC calls:

- counting the number of sockets
- counting the number of clusters in one socket
- counting the number of cores in one cluster
- counting the number of threads in one core

Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Change-Id: I0059a5c7bb7055aba1aa5ec5bfd0ec78801874f8

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fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 G

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 GPT table. Add two pages to the L0 GPT reserve.
This could be optimized later by moving the bitlock somewhere else,
because it really only needs (1 << PPS.T) / (512M * 8) = 256 bytes for
the QEMU virt platform.

Fix two more comments in qemu_pas_def.h since we're here.

Change-Id: I2b0b8de38f4b5058735ed16f1cdc50e6b2d52ad9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables

build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).

These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:

make --silent V=1

... results in a silent build.

In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.

When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed but not echoed'

When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed and echoed'

In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:

$(s)echo 'This command is executed but not echoed'
$(q)echo 'This command is executed but not echoed'

The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.

Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This is not a problem when loading boot images as the
lower addresses are the same. However, it can be a problem when starting
up the secondary CPUs with a rather high non-secure entry point. So fix
this by removing the plat_psci_ops_t validate_ns_entrypoint assignment
to allow any non-secure entry point.

Change-Id: I95e92b71e0f4fa5f94444ea0cd2cb42e56faa472
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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refactor(qemu): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software compon

refactor(qemu): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software components, and to
provide a more realistic breakdown of the expected components in the CCA
TCB.

This change replaces the static CCA platform token in QEMU.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I8ce49e6ecf83c426dee9024e782a8da457316959
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>

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refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all th

refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:

-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability

The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.

- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.

Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fv

Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'

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feat(qemu): update to manifest v0.3

Update the RMM manifest to v0.3: pass the console information to RMM.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Change-Id: I55093cd0c12f9c6

feat(qemu): update to manifest v0.3

Update the RMM manifest to v0.3: pass the console information to RMM.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Change-Id: I55093cd0c12f9c6a7569d7e524f7d301acbb2a45

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Merge "feat(qemu): allow ARM_ARCH_MAJOR/MINOR override" into integration

Merge "feat(qemu): enable FEAT_ECV when present" into integration

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPD

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
> In Armv8.6, the architecture standardized this frequency to 1GHz.

This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
cores and 1GHz on newer ones.

Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-I

refactor(qemu): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I2c6840f6f3f2f8f64595a0e0aa6e12084a37ce6e

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