Tegra: remove ENABLE_SVE_FOR_NS = 0

The SVE CPU extension library reads the id_aa64pfr0_el1 register to
check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for
pre-8.2 platforms, but

Tegra: remove ENABLE_SVE_FOR_NS = 0

The SVE CPU extension library reads the id_aa64pfr0_el1 register to
check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for
pre-8.2 platforms, but this flag can safely be enabled now that the
library can enable the feature at runtime.

This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0"
as a result.

Change-Id: Ia2a89ac90644f8c0d39b41d321e04458ff6be6e1
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

show more ...

Tegra194: remove unused tegra_mc_defs header

This patch removes the unused header from the Tegra194
platform files. As a result, the TSA MMIO would be
removed from the memory map too.

Change-Id: I2

Tegra194: remove unused tegra_mc_defs header

This patch removes the unused header from the Tegra194
platform files. As a result, the TSA MMIO would be
removed from the memory map too.

Change-Id: I2d38b3da7a119f5dfd6cfd429e481f4e6ad3481e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: memctrl: platform setup handler functions

The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver rema

Tegra: memctrl: platform setup handler functions

The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver remains generic enough, some code should be moved
to SoC.

This patch creates a setup handler for a platform to implement its
initialization sequence.

Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra194: memctrl: remove streamid security cfg registers

The stream ID security configuration settings shall be done by the
previous level bootloader. This change removes the same settings
from the

Tegra194: memctrl: remove streamid security cfg registers

The stream ID security configuration settings shall be done by the
previous level bootloader. This change removes the same settings
from the Tegra194 platform code as a result.

Change-Id: Ia170ca4c2119db8f1d0251f1c193add006f81004
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

show more ...

Tegra194: memctrl: remove streamid override cfg registers

The stream ID override configuration is saved during System Suspend
as part MB1 bct. This change removes the same support from the Tegra194

Tegra194: memctrl: remove streamid override cfg registers

The stream ID override configuration is saved during System Suspend
as part MB1 bct. This change removes the same support from the Tegra194
platform code as a result.

Change-Id: I4c19dc0d8b29190908673fb5ed7ed892af8906ab
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

show more ...

Tegra: debug prints indicating SC7 entry sequence completion

This patch adds prints to display the completion of System Suspend
programming sequence for Tegra platforms. The console needs to
be kept

Tegra: debug prints indicating SC7 entry sequence completion

This patch adds prints to display the completion of System Suspend
programming sequence for Tegra platforms. The console needs to
be kept alive until the very end of the System Suspend sequence as
a result.

Change-Id: I8e0e2054a272665d0a067bb894dda1605a9d2eb7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra194: add strict checking mode verification

After enabling the strict checking mode, verify that
the strict mode has really been enabled by querying
the MCE.

If the mode is found to be disabled

Tegra194: add strict checking mode verification

After enabling the strict checking mode, verify that
the strict mode has really been enabled by querying
the MCE.

If the mode is found to be disabled, the code should
assert.

Change-Id: I113ec8decb737f8208059a2a3ba3076fad77890e
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

show more ...

Tegra194: memctrl: update TZDRAM base at 1MB granularity

The Memory controller expects the TZDRAM base value at 1MB granularity
and the current driver does not respect that limitation. This patch
fi

Tegra194: memctrl: update TZDRAM base at 1MB granularity

The Memory controller expects the TZDRAM base value at 1MB granularity
and the current driver does not respect that limitation. This patch
fixes that anomaly.

Change-Id: I6b72270f331ba5081e19811df4a78623e457341a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra194: ras: split up RAS error clear SMC call.

In order to make sure SMC call is within 25us, this patch reduces number of RAS
errors accessed to 8 at most for each SMC call and takes a input/out

Tegra194: ras: split up RAS error clear SMC call.

In order to make sure SMC call is within 25us, this patch reduces number of RAS
errors accessed to 8 at most for each SMC call and takes a input/output
parameter to specify in progress RAS error record index.

The measured SMC call latency is about 20us under Linux test kernel driver.

Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f
Signed-off-by: David Pu <dpu@nvidia.com>

show more ...

Tegra: platform specific GIC sources

The TEGRA_GICv2_SOURCES contains the list of GIC sources required
to compile the GICv2 support for platforms.

This patch includes the TEGRA_GICv2_SOURCES macro

Tegra: platform specific GIC sources

The TEGRA_GICv2_SOURCES contains the list of GIC sources required
to compile the GICv2 support for platforms.

This patch includes the TEGRA_GICv2_SOURCES macro from individual
makefiles to allow future platforms to use suport for GICv3.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I429b1a0c7764ab370675f873a50cecda871110cb

show more ...

Tegra194: add memory barriers during DRAM to SysRAM copy

This patch adds memory barriers to the trampoline code copying TZDRAM
contents to SysRAM during exit from System Suspend. These barriers
make

Tegra194: add memory barriers during DRAM to SysRAM copy

This patch adds memory barriers to the trampoline code copying TZDRAM
contents to SysRAM during exit from System Suspend. These barriers
make sure that all the copies go through before we start executing in
SysRAM.

Reported by: Nathan Tuck <ntuck@nvidia.com>

Change-Id: I3fd2964086b6c0e044cc4165051a4801440db9cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: sip: add VPR resize enabled check

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which

Tegra: sip: add VPR resize enabled check

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.

This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.

Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

show more ...

Tegra194: add redundancy checks for MMIO writes

MMIO writes should verify that the writes actually went through.
Read the value back after the write operation, perform assert
if the read back value

Tegra194: add redundancy checks for MMIO writes

MMIO writes should verify that the writes actually went through.
Read the value back after the write operation, perform assert
if the read back value is not same as the write value.

Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

show more ...

Tegra: remove unused cortex_a53.h

This patch removes the unused cortex_a53.h header file from
common Tegra files.

This change fixes the violation of CERTC Rule: DCL23.

Change-Id: Iaf7c34cc6323b780

Tegra: remove unused cortex_a53.h

This patch removes the unused cortex_a53.h header file from
common Tegra files.

This change fixes the violation of CERTC Rule: DCL23.

Change-Id: Iaf7c34cc6323b78028258e188c00724c52afba85
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra194: report failure to enable dual execution

During boot the platform enables dual execution for Xavier CPUs.
This patch reads back the ACTLR_ELx register to verify that the bit
is actually set

Tegra194: report failure to enable dual execution

During boot the platform enables dual execution for Xavier CPUs.
This patch reads back the ACTLR_ELx register to verify that the bit
is actually set. It asserts if the bit is not set.

Change-Id: I5ba9491ced86285d307b95efa647a427ff77c79e
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

show more ...

Tegra194: verify firewall settings before resource use

The firewall settings for the hardware resources are present in the
Security Configuration Registers. The firewall settings are programmed
by o

Tegra194: verify firewall settings before resource use

The firewall settings for the hardware resources are present in the
Security Configuration Registers. The firewall settings are programmed
by other software components and so must be verified for correctness
before touching the hardware resources they protect.

This patch reads the firewall settings during early boot and asserts
if the settings mismatch.

Change-Id: I53cc9aeadad32e54e460db0fa2c38e46bcc92066
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Merge changes from topic "tegra194-spmd" into integration

* changes:
Tegra194: introduce support for `SPD=spmd`
Tegra: introduce backend support to compile libfdt
Tegra: disable signed compari

Merge changes from topic "tegra194-spmd" into integration

* changes:
Tegra194: introduce support for `SPD=spmd`
Tegra: introduce backend support to compile libfdt
Tegra: disable signed comparison
plat: common: include "bl_common.h" from plat_spmd_manifest.c

show more ...

Tegra194: introduce support for `SPD=spmd`

This patch introduces the following changes to enable
compilation for `SPD=spmd` command line option.

* compile plat_spmd_manifest.c
* compile libfdt sour

Tegra194: introduce support for `SPD=spmd`

This patch introduces the following changes to enable
compilation for `SPD=spmd` command line option.

* compile plat_spmd_manifest.c
* compile libfdt source files

Verified with the `SPD=spmd` command line option for
Tegra194 platforms.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I7f57aa4f1756b19f78d87415bb80794417174bc8

show more ...

Tegra: introduce backend support to compile libfdt

This patch includes the following files from libc to
compile libfdt:

* memchr.c
* memcmp.c
* strrchr.c

The BUILD_PLAT macro is evaluated earlier

Tegra: introduce backend support to compile libfdt

This patch includes the following files from libc to
compile libfdt:

* memchr.c
* memcmp.c
* strrchr.c

The BUILD_PLAT macro is evaluated earlier to allow libfdt
installation to the right directory.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ie43fcf701dc051670e6372e21b3a84a6416c1735

show more ...

Tegra: disable signed comparison

libfdt does not support the -Wsign-compare compiler option
and the right patch will eventually be pushed upstream.

This patch disables the -Wsign-compare compiler o

Tegra: disable signed comparison

libfdt does not support the -Wsign-compare compiler option
and the right patch will eventually be pushed upstream.

This patch disables the -Wsign-compare compiler option
to allow libfdt compilation for Tegra platforms until
the actual issue is fixed.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib7a93946cad1ea9ec1b46751edb79a74c08ed0ac

show more ...

Tegra194: remove AON_WDT IRQ mapping

This patch removes the unused interrupt mapping for AON_WDT
for all Tegra194 platforms.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I475a1e83f

Tegra194: remove AON_WDT IRQ mapping

This patch removes the unused interrupt mapping for AON_WDT
for all Tegra194 platforms.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I475a1e83f809c740e62464b5b4e93cb0a2e33d6b

show more ...

Tegra: smmu: add smmu_verify function

The SMMU configuration can get corrupted or updated by
external clients during boot without our knowledge.

This patch introduces a "verify" function for the SM

Tegra: smmu: add smmu_verify function

The SMMU configuration can get corrupted or updated by
external clients during boot without our knowledge.

This patch introduces a "verify" function for the SMMU
driver, to check that the boot configuration settings are
intact. Usually, this function should be called at the
end of the boot cycle.

This function only calls panic() on silicon platforms.

Change-Id: I2ab45a7f228781e71c73ba1f4ffc49353effe146
Signed-off-by: George Bauernschmidt <georgeb@nvidia.com>

show more ...

Tegra: TZDRAM setup from soc specific early_boot handlers

TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in th

Tegra: TZDRAM setup from soc specific early_boot handlers

TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in the
newer chips.

This patch moves the TZDRAM setup to early_boot handlers for SoCs to
handle this scenario.

Change-Id: I6481b4f848a4dadc20cb83852cd8e19a242b3a34
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: remove "platform_get_core_pos" function

This patch removes the deprecated 'plat_core_pos_by_mpidr' function
from the Tegra platform port.

Change-Id: I32e06cb7269e4fbfaf9ad6c26d0722201f982f9e

Tegra: remove "platform_get_core_pos" function

This patch removes the deprecated 'plat_core_pos_by_mpidr' function
from the Tegra platform port.

Change-Id: I32e06cb7269e4fbfaf9ad6c26d0722201f982f9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: print GICC registers conditionally

The GICC interface exists only on the interrupt controllers following
the GICv2 specification.

This patch prints the GICC register contents from the platfo

Tegra: print GICC registers conditionally

The GICC interface exists only on the interrupt controllers following
the GICv2 specification.

This patch prints the GICC register contents from the platform's macro,
plat_crash_print_regs' only when TEGRA_GICC_BASE is defined. This
allows platforms using future versions of the GIC specification to
still use this macro.

Change-Id: Ia5762d0a1ae28c832664d69362a7776e46a22ad1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...