| de4a6438 | 20-Dec-2017 |
Vignesh Radhakrishnan <vigneshr@nvidia.com> |
Tegra194: request CG7 before checking if SC7 is allowed
Currently firmware seems to be checking if we can get into system
suspend after checking if CC6 & C7 is allowed. For system suspend
to be trig
Tegra194: request CG7 before checking if SC7 is allowed
Currently firmware seems to be checking if we can get into system
suspend after checking if CC6 & C7 is allowed. For system suspend
to be triggered, the firmware needs to request for CG7 as well.
This patch fixes this anomaly.
Change-Id: I39c4c50092a4288f4f3fa4b0b1d5026be50f058f
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| a3c2c0e9 | 12-Dec-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: config to enable/disable strict checking mode
This patch adds a new configuration option to the platform makefiles
that disables/enables strict checking mode. The config is enabled
by defa
Tegra194: config to enable/disable strict checking mode
This patch adds a new configuration option to the platform makefiles
that disables/enables strict checking mode. The config is enabled
by default.
Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb
Signed-off-by: Steven Kao <skao@nvidia.com>
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| 181a9fab | 29-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: remove unused platform configs
This patch cleans the makefile to remove unused platform config
options.
Change-Id: I96d9795c0f0ba593de96017dc9a401d7c2ab471a
Signed-off-by: Varun Wadekar <
Tegra194: remove unused platform configs
This patch cleans the makefile to remove unused platform config
options.
Change-Id: I96d9795c0f0ba593de96017dc9a401d7c2ab471a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 26c1a1e7 | 21-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: restore XUSB stream IDs on System Resume
The stream IDs for XUSB programmed during cold boot are lost on System
Suspend. This patch restores the XUSB stream IDs on System Resume.
NOTE: TH
Tegra194: restore XUSB stream IDs on System Resume
The stream IDs for XUSB programmed during cold boot are lost on System
Suspend. This patch restores the XUSB stream IDs on System Resume.
NOTE: THE WARMBOOT CODE NEEDS TO MAKE SURE THAT THE XUSB MODULE IS OUT
OF RESET AND THE CLOCKS ARE ENABLED, BEFORE POWERING ON THE CPU, DURING
SYSTEM RESUME.
Change-Id: Ibd5f1e5ebacffa6b29b625f4c41ecf204afa8191
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 22c72f2a | 09-Jan-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: drivers: fix violations of MISRA Rule 21.1
This patch fixes the violations of Rule 21.1 from all the
header files.
Rule 21.1 "#define and #undef shall not be used on a reserved
Tegra194: drivers: fix violations of MISRA Rule 21.1
This patch fixes the violations of Rule 21.1 from all the
header files.
Rule 21.1 "#define and #undef shall not be used on a reserved
identifier or reserved macro name"
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc
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| 13be0ee4 | 10-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: nvidia: remove spurious UTF-8 characters at top of platform files" into integration |
| 1ab2dc1a | 09-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Remove redundant declarations." into integration |
| f1f72019 | 09-Jan-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
plat: nvidia: remove spurious UTF-8 characters at top of platform files
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423 |
| 7a05f06a | 02-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Remove redundant declarations.
In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.
Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by:
Remove redundant declarations.
In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.
Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| e1fcb1bf | 03-Jan-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: mce: fix error code signedness
The MCE driver's helper functions were using postive values as error
codes.
This patch updates the functions to return negative values as error
codes instea
Tegra194: mce: fix error code signedness
The MCE driver's helper functions were using postive values as error
codes.
This patch updates the functions to return negative values as error
codes instead. Some functions are updated to use the right error code.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6
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| fba54d55 | 26-Oct-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: smmu: add support for backup multiple smmu regs
Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Susp
Tegra194: smmu: add support for backup multiple smmu regs
Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Suspend state.
Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| 4719bba9 | 03-Dec-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: psci: rename 'percpu_data' variable
The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspel
Tegra194: psci: rename 'percpu_data' variable
The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspelt.
This patch fixes this typographical error to fix compilation errors.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735
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| 95397d96 | 30-Nov-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: memctrl: fix logic to check TZDRAM config register access
This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The pola
Tegra194: memctrl: fix logic to check TZDRAM config register access
This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.
Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: Steven Kao <skao@nvidia.com>
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|
| 117dbe6c | 21-Aug-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: introduce plat_enable_console()
This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while a
Tegra: introduce plat_enable_console()
This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.
For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.
Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 02b3e311 | 08-Nov-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: update nvg header to v6.4
This patch updates the header, t194_nvg.h, to v6.4. This
gets it in synch with MTS pre-release 2 - cl39748439.
Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ec
Tegra194: update nvg header to v6.4
This patch updates the header, t194_nvg.h, to v6.4. This
gets it in synch with MTS pre-release 2 - cl39748439.
Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7
Signed-off-by: Steven Kao <skao@nvidia.com>
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|
| ac252f95 | 10-Aug-2017 |
Dilan Lee <dilee@nvidia.com> |
Tegra194: mce: enable strict checking
"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure
Tegra194: mce: enable strict checking
"Strict checking" is a mode where secure world can access
secure-only areas unlike legacy mode where secure world could
access non-secure spaces as well. Secure-only areas are defined
as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set.
This mode not only helps prevent issues with IO-Coherency but aids
with security as well.
This patch implements the programming sequence required to enable
strict checking mode for Tegra194 SoCs.
Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0
Signed-off-by: Dilan Lee <dilee@nvidia.com>
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|
| 1b0f027d | 16-Oct-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: CC6 state from last offline CPU in the cluster
This patch enables the CC6 cluster state for the cluster, if the
current CPU being offlined is the last CPU in the cluster.
Change-Id: I3380
Tegra194: CC6 state from last offline CPU in the cluster
This patch enables the CC6 cluster state for the cluster, if the
current CPU being offlined is the last CPU in the cluster.
Change-Id: I3380a969b534fcd14f9c46433471cc1c2adf6011
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 14f52852 | 15-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: console driver compilation from platform makefiles
This patch includes the console driver from individual platform
makefile, to allow future platforms to include consoles of their
choice.
Tegra194: console driver compilation from platform makefiles
This patch includes the console driver from individual platform
makefile, to allow future platforms to include consoles of their
choice.
Change-Id: I4c92199717da410c8b5e8d45af67f4345f743dbd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 4e697b77 | 14-Nov-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: memctrl: platform handler for TZDRAM setup
This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers
Tegra194: memctrl: platform handler for TZDRAM setup
This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers are locked and TZDRAM setup has already been done by the
previous bootloaders, before setting up the fence.
Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3
Signed-off-by: Steven Kao <skao@nvidia.com>
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|
| 5ad50d7d | 08-Sep-2017 |
Puneet Saxena <puneets@nvidia.com> |
Tegra194: memctrl: override SE client as coherent
This patch enables IO coherency for SE clients, SEWR and SERD,
by overriding their platform settings to "normal_coherent".
This setting also convert
Tegra194: memctrl: override SE client as coherent
This patch enables IO coherency for SE clients, SEWR and SERD,
by overriding their platform settings to "normal_coherent".
This setting also converts read/write requests from these SE
clients to Normal type.
Change-Id: I31ad195ad30ecc9ee785e5e84184cda2eea5c45a
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Signed-off-by: Jeff Tsai <jefft@nvidia.com>
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|
| 040529e9 | 10-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: save system suspend entry marker to TZDRAM
This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is
Tegra194: save system suspend entry marker to TZDRAM
This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.
The Tegra194 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.
Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 653fc380 | 10-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: helper functions for CPU rst handler and SMMU ctx offset
This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offse
Tegra194: helper functions for CPU rst handler and SMMU ctx offset
This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.
Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 1c62509e | 10-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: cleanup references to Tegra186
This patch cleans up all references to the Tegra186 family of SoCs.
Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: Varun Wadekar <vwade
Tegra194: cleanup references to Tegra186
This patch cleans up all references to the Tegra186 family of SoCs.
Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| ac2cc6b0 | 07-Nov-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: mce: display NVG header version during boot
The MCE driver checks the NVG interface version during boot and
disaplys the hardware and software versions on the console. The
software version
Tegra194: mce: display NVG header version during boot
The MCE driver checks the NVG interface version during boot and
disaplys the hardware and software versions on the console. The
software version is being displayed as zero.
This patch updates the prints to use the real NVG header version
instead.
Change-Id: I8e9d2e6c43a59a8a6d5ca7aa8153b940fce86709
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 4b412b50 | 04-Nov-2017 |
Vignesh Radhakrishnan <vigneshr@nvidia.com> |
Tegra194: mce: fix cg_cstate encoding format
This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9
Tegra194: mce: fix cg_cstate encoding format
This patch does the following:
- cstate_info variable is used to pass on requested cstate to mce
- Currently, cg_cstate is encoded using 2 bits(bits 8, 9) in cstate_info
- cg_cstate values can range from 0 to 7, with 7 representing cg7
- Thus, cg_cstate is to be encoded using 3 bits (val: 0-7)
- Fix this, as per ISS and ensure bits 8, 9, 10 are used
Change-Id: Idff207e2a88b2f4654e4a956c27054bf5e8f69bb
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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|