1# 2# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# platform configs 8ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 0 9$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) 10 11RELOCATE_TO_BL31_BASE := 1 12$(eval $(call add_define,RELOCATE_TO_BL31_BASE)) 13 14ENABLE_CHIP_VERIFICATION_HARNESS := 0 15$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) 16 17ENABLE_SMMU_DEVICE := 1 18$(eval $(call add_define,ENABLE_SMMU_DEVICE)) 19 20RESET_TO_BL31 := 1 21 22PROGRAMMABLE_RESET_ADDRESS := 1 23 24COLD_BOOT_SINGLE_CPU := 1 25 26# platform settings 27TZDRAM_BASE := 0x40000000 28$(eval $(call add_define,TZDRAM_BASE)) 29 30PLATFORM_CLUSTER_COUNT := 4 31$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 32 33PLATFORM_MAX_CPUS_PER_CLUSTER := 2 34$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 35 36MAX_XLAT_TABLES := 25 37$(eval $(call add_define,MAX_XLAT_TABLES)) 38 39MAX_MMAP_REGIONS := 30 40$(eval $(call add_define,MAX_MMAP_REGIONS)) 41 42# platform files 43PLAT_INCLUDES += -I${SOC_DIR}/drivers/include 44 45BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ 46 lib/cpus/aarch64/denver.S \ 47 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 48 ${COMMON_DIR}/drivers/smmu/smmu.c \ 49 ${SOC_DIR}/drivers/mce/mce.c \ 50 ${SOC_DIR}/drivers/mce/nvg.c \ 51 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 52 ${SOC_DIR}/drivers/se/se.c \ 53 ${SOC_DIR}/plat_memctrl.c \ 54 ${SOC_DIR}/plat_psci_handlers.c \ 55 ${SOC_DIR}/plat_setup.c \ 56 ${SOC_DIR}/plat_secondary.c \ 57 ${SOC_DIR}/plat_sip_calls.c \ 58 ${SOC_DIR}/plat_smmu.c \ 59 ${SOC_DIR}/plat_trampoline.S 60