1# 2# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# platform configs 8ENABLE_CONSOLE_SPE := 0 9$(eval $(call add_define,ENABLE_CONSOLE_SPE)) 10 11RESET_TO_BL31 := 1 12 13PROGRAMMABLE_RESET_ADDRESS := 1 14 15COLD_BOOT_SINGLE_CPU := 1 16 17# platform settings 18TZDRAM_BASE := 0x40000000 19$(eval $(call add_define,TZDRAM_BASE)) 20 21PLATFORM_CLUSTER_COUNT := 4 22$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 23 24PLATFORM_MAX_CPUS_PER_CLUSTER := 2 25$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 26 27MAX_XLAT_TABLES := 25 28$(eval $(call add_define,MAX_XLAT_TABLES)) 29 30MAX_MMAP_REGIONS := 30 31$(eval $(call add_define,MAX_MMAP_REGIONS)) 32 33# platform files 34PLAT_INCLUDES += -I${SOC_DIR}/drivers/include 35 36BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ 37 lib/cpus/aarch64/denver.S \ 38 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \ 39 ${COMMON_DIR}/drivers/smmu/smmu.c \ 40 ${SOC_DIR}/drivers/mce/mce.c \ 41 ${SOC_DIR}/drivers/mce/nvg.c \ 42 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 43 ${SOC_DIR}/drivers/se/se.c \ 44 ${SOC_DIR}/plat_memctrl.c \ 45 ${SOC_DIR}/plat_psci_handlers.c \ 46 ${SOC_DIR}/plat_setup.c \ 47 ${SOC_DIR}/plat_secondary.c \ 48 ${SOC_DIR}/plat_sip_calls.c \ 49 ${SOC_DIR}/plat_smmu.c \ 50 ${SOC_DIR}/plat_trampoline.S 51 52ifeq (${ENABLE_CONSOLE_SPE},1) 53BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S 54endif 55