1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl31/bl31.h> 10 #include <common/bl_common.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <context.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <cortex_a57.h> 16 #include <common/debug.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <bl31/interrupt_mgmt.h> 21 #include <mce.h> 22 #include <mce_private.h> 23 #include <plat/common/platform.h> 24 #include <tegra_def.h> 25 #include <tegra_mc_def.h> 26 #include <tegra_platform.h> 27 #include <tegra_private.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 30 /******************************************************************************* 31 * The Tegra power domain tree has a single system level power domain i.e. a 32 * single root node. The first entry in the power domain descriptor specifies 33 * the number of power domains at the highest power level. 34 ******************************************************************************* 35 */ 36 static const uint8_t tegra_power_domain_tree_desc[] = { 37 /* No of root nodes */ 38 1, 39 /* No of clusters */ 40 PLATFORM_CLUSTER_COUNT, 41 /* No of CPU cores - cluster0 */ 42 PLATFORM_MAX_CPUS_PER_CLUSTER, 43 /* No of CPU cores - cluster1 */ 44 PLATFORM_MAX_CPUS_PER_CLUSTER, 45 /* No of CPU cores - cluster2 */ 46 PLATFORM_MAX_CPUS_PER_CLUSTER, 47 /* No of CPU cores - cluster3 */ 48 PLATFORM_MAX_CPUS_PER_CLUSTER 49 }; 50 51 /******************************************************************************* 52 * This function returns the Tegra default topology tree information. 53 ******************************************************************************/ 54 const uint8_t *plat_get_power_domain_tree_desc(void) 55 { 56 return tegra_power_domain_tree_desc; 57 } 58 59 /* 60 * Table of regions to map using the MMU. 61 */ 62 static const mmap_region_t tegra_mmap[] = { 63 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ 64 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 65 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ 66 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 67 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ 68 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ 70 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ 72 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ 74 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ 76 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ 78 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ 80 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ 82 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ 84 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ 86 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ 88 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ 90 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ 92 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ 94 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ 96 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 97 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */ 98 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 99 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */ 100 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 101 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */ 102 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), 103 {0} 104 }; 105 106 /******************************************************************************* 107 * Set up the pagetables as per the platform memory map & initialize the MMU 108 ******************************************************************************/ 109 const mmap_region_t *plat_get_mmio_map(void) 110 { 111 /* MMIO space */ 112 return tegra_mmap; 113 } 114 115 /******************************************************************************* 116 * Handler to get the System Counter Frequency 117 ******************************************************************************/ 118 uint32_t plat_get_syscnt_freq2(void) 119 { 120 return 31250000; 121 } 122 123 /******************************************************************************* 124 * Maximum supported UART controllers 125 ******************************************************************************/ 126 #define TEGRA194_MAX_UART_PORTS 7 127 128 /******************************************************************************* 129 * This variable holds the UART port base addresses 130 ******************************************************************************/ 131 static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = { 132 0, /* undefined - treated as an error case */ 133 TEGRA_UARTA_BASE, 134 TEGRA_UARTB_BASE, 135 TEGRA_UARTC_BASE, 136 TEGRA_UARTD_BASE, 137 TEGRA_UARTE_BASE, 138 TEGRA_UARTF_BASE, 139 TEGRA_UARTG_BASE 140 }; 141 142 /******************************************************************************* 143 * Retrieve the UART controller base to be used as the console 144 ******************************************************************************/ 145 uint32_t plat_get_console_from_id(int32_t id) 146 { 147 uint32_t ret; 148 149 if (id > TEGRA194_MAX_UART_PORTS) { 150 ret = 0; 151 } else { 152 ret = tegra194_uart_addresses[id]; 153 } 154 155 return ret; 156 } 157 158 /******************************************************************************* 159 * Handler for early platform setup 160 ******************************************************************************/ 161 void plat_early_platform_setup(void) 162 { 163 164 /* sanity check MCE firmware compatibility */ 165 mce_verify_firmware_version(); 166 167 /* Program XUSB STREAMIDs 168 * Xavier XUSB has support for XUSB virtualization. It will have one 169 * physical function (PF) and four Virtual function (VF) 170 * 171 * There were below two SIDs for XUSB until T186. 172 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU 173 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU 174 * 175 * We have below four new SIDs added for VF(s) 176 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU 177 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU 178 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU 179 * 6) #define TEGRA_SID_XUSB_VF3 0x60U 180 * 181 * When virtualization is enabled then we have to disable SID override 182 * and program above SIDs in below newly added SID registers in XUSB 183 * PADCTL MMIO space. These registers are TZ protected and so need to 184 * be done in ATF. 185 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) 186 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) 187 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) 188 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) 189 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) 190 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) 191 * 192 * This change disables SID override and programs XUSB SIDs in 193 * above registers to support both virtualization and non-virtualization 194 * 195 * Known Limitations: 196 * If xusb interface disables SMMU in XUSB DT in non-virtualization 197 * setup then there will be SMMU fault. We need to use WAR at 198 * https:\\git-master.nvidia.com/r/1529227/ to the issue. 199 * 200 * More details can be found in the bug 1971161 201 */ 202 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 203 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST); 204 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 205 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0); 206 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 207 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1); 208 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 209 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2); 210 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 211 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3); 212 mmio_write_32(TEGRA_XUSB_PADCTL_BASE + 213 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV); 214 } 215 216 /* Secure IRQs for Tegra194 */ 217 static const interrupt_prop_t tegra194_interrupt_props[] = { 218 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 219 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 220 INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 221 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 222 }; 223 224 /******************************************************************************* 225 * Initialize the GIC and SGIs 226 ******************************************************************************/ 227 void plat_gic_setup(void) 228 { 229 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props)); 230 tegra_gic_init(); 231 232 /* 233 * Initialize the FIQ handler 234 */ 235 tegra_fiq_handler_setup(); 236 } 237 238 /******************************************************************************* 239 * Return pointer to the BL31 params from previous bootloader 240 ******************************************************************************/ 241 struct tegra_bl31_params *plat_get_bl31_params(void) 242 { 243 uint32_t val; 244 245 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); 246 247 return (struct tegra_bl31_params *)(uintptr_t)val; 248 } 249 250 /******************************************************************************* 251 * Return pointer to the BL31 platform params from previous bootloader 252 ******************************************************************************/ 253 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 254 { 255 uint32_t val; 256 257 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); 258 259 return (plat_params_from_bl2_t *)(uintptr_t)val; 260 } 261 262 void plat_late_platform_setup(void) 263 { 264 /* 265 * Enable strict checking after programming the GSC for 266 * enabling TZSRAM and TZDRAM 267 */ 268 mce_enable_strict_checking(); 269 } 270