| 8ca61538 | 18-Mar-2019 |
David Pu <dpu@nvidia.com> |
Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to
handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9
Sign
Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to
handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9
Signed-off-by: David Pu <dpu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| d886628d | 18-Apr-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: enable SDEI handling
This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.
* SGI 8 as the source IRQ
* Special Private Event 0
* Three private,
Tegra: enable SDEI handling
This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.
* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events
Verified using TFTF SDEI test suite.
******************************* Summary *******************************
Test suite 'SDEI' Passed
=================================
Tests Skipped : 0
Tests Passed : 5
Tests Failed : 0
Tests Crashed : 0
Total tests : 5
=================================
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390
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| b5b2923d | 12-May-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: introduce support for SMCCC_ARCH_SOC_ID
This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.
Verified using TFTF SMCCC
Tegra: introduce support for SMCCC_ARCH_SOC_ID
This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.
Verified using TFTF SMCCC_ARCH_SOC_ID test.
<snip>
> Executing 'SMCCC_ARCH_SOC_ID test'
TEST COMPLETE Passed
SOC Rev = 0x102
SOC Ver = 0x36b0019
<snip>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibd7101619143b74f6f6660732daeac1a8bca3e44
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| adb20a17 | 01-Apr-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: enable EHF for watchdog timer interrupts
This patch enables the Exception Handling Framework to service the WDT
interrupts on all Tegra platforms.
Verified that the watchdog timer interrupt
Tegra: enable EHF for watchdog timer interrupts
This patch enables the Exception Handling Framework to service the WDT
interrupts on all Tegra platforms.
Verified that the watchdog timer interrupt fires after migrating to
the EHF.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I6b2e33da7841aa064e3a8f825c26fadf168cd0d5
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| 9aaa8882 | 11-Mar-2019 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra194: move cluster and CPU counter to header file.
MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cann
Tegra194: move cluster and CPU counter to header file.
MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cannot be done.
This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER
macros to tegra_def.h as a result.
Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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| 71376951 | 24-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl_v2: remove support to secure TZSRAM
This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.
Tegra: memctrl_v2: remove support to secure TZSRAM
This patch removes support to secure the on-chip TZSRAM memory for
Tegra186 and Tegra194 platforms as the previous bootloader does that
for them.
Change-Id: I50c7b7f9694285fe31135ada09baed1cfedaaf07
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 42080d48 | 21-Dec-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: remove circular dependency with common_def.h
This patch stops including common_def.h from platform_def.h to
fix a circular depoendency between them.
This means platform_def.h now has to defi
Tegra: remove circular dependency with common_def.h
This patch stops including common_def.h from platform_def.h to
fix a circular depoendency between them.
This means platform_def.h now has to define the linker macros:
* PLATFORM_LINKER_FORMAT
* PLATFORM_LINKER_ARCH
Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| a5bfcad8 | 21-Dec-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: include missing stdbool.h
This patch includes the missing stdbool.h header from flowctrl.h
and bpmp_ivc.c files.
Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2
Signed-off-by: Varun Wad
Tegra: include missing stdbool.h
This patch includes the missing stdbool.h header from flowctrl.h
and bpmp_ivc.c files.
Change-Id: If60d19142b1cb8ae663fbdbdf1ffe45cbbdbc1b2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 2bf1085d | 19-Dec-2018 |
Kalyani Chidambaram <kalyanic@nvidia.com> |
Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.
This patch uses the common macros provided by bl_common.h as a result
and add
Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
Tegra platforms will not be supporting SEPARATE_CODE_AND_RODATA=0.
This patch uses the common macros provided by bl_common.h as a result
and adds a check to assert if SEPARATE_CODE_AND_RODATA set is not set
to '1'.
Change-Id: I376ea60c00ad69cb855d89418bdb80623f14800e
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
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| 2139c9c8 | 09-Nov-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: system resume from TZSRAM memory
TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores t
Tegra186: system resume from TZSRAM memory
TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores the contents to TZSRAM during System Resume.
This patch removes the code that sets up CPU vector to point to
TZSRAM during System Resume as a result. The trampoline code can
also be completely removed as a result.
Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 8336c94d | 09-Aug-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the abi
Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.
Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| d55b8f6a | 12-Sep-2018 |
Kalyani Chidambaram <kalyanic@nvidia.com> |
Tegra194: enable dual execution for EL2 and EL3
This patch enables dual execution optimized translations for EL2 and EL3
CPU exception levels.
Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1
S
Tegra194: enable dual execution for EL2 and EL3
This patch enables dual execution optimized translations for EL2 and EL3
CPU exception levels.
Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| f8827c60 | 10-Aug-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra210: support for secure physical timer
This patch enables on-chip timer1 interrupts for Tegra210 platforms.
Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: Varun Wadekar <v
Tegra210: support for secure physical timer
This patch enables on-chip timer1 interrupts for Tegra210 platforms.
Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 91dd7edd | 10-Dec-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: smmu: export handlers to read/write SMMU registers
This patch exports the SMMU register read/write handlers for platforms.
Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by:
Tegra: smmu: export handlers to read/write SMMU registers
This patch exports the SMMU register read/write handlers for platforms.
Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| a391d494 | 03-Aug-2018 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra: smmu: remove context save sequence
SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS
Tegra: smmu: remove context save sequence
SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.
This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.
Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| e9044480 | 13-Sep-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194
This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, wa
Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194
This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.
Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 029dd14e | 06-Jul-2018 |
Jeetesh Burman <jburman@nvidia.com> |
Tegra194: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
s
Tegra194: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.
This patch adds driver for the SE engine, with APIs to calculate the hash
and store to PMC scratch registers.
Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
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| 2ac7b223 | 06-Jul-2018 |
Jeetesh Burman <jburman@nvidia.com> |
Tegra194: store TZDRAM base/size to scratch registers
This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify in
Tegra194: store TZDRAM base/size to scratch registers
This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.
Change-Id: I2f5fd11c87804d20e2698de33be977991c9f6f33
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
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| 4eed9c84 | 19-Jul-2018 |
Jeetesh Burman <jburman@nvidia.com> |
Tegra186: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
s
Tegra186: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.
This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.
Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
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| 3827aa8a | 31-May-2018 |
Jeetesh Burman <jburman@nvidia.com> |
Tegra186: add support for bpmp_ipc driver
This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.
Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818a
Tegra186: add support for bpmp_ipc driver
This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.
Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
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| 41554fb2 | 10-Apr-2018 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra210: SE: add context save support
Tegra210B01 SoCs support atomic context save for the two SE
hardware engines. Tegra210 SoCs have support for only one SE
engine and support a software based sa
Tegra210: SE: add context save support
Tegra210B01 SoCs support atomic context save for the two SE
hardware engines. Tegra210 SoCs have support for only one SE
engine and support a software based save/restore mechanism
instead.
This patch updates the SE driver to make this change.
Change-Id: Ia5e5ed75d0fe011f17809684bbc2ed2338925946
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
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| 24902fae | 19-Jun-2018 |
kalyani chidambaram <kalyanic@nvidia.com> |
Tegra210: update the PMC blacklisted registers
Update the list to include PMC registers that the NS world cannot
access even with smc calls.
Change-Id: I588179b56ebc0c29200b55e6d61535fd3a7a3b7e
Sig
Tegra210: update the PMC blacklisted registers
Update the list to include PMC registers that the NS world cannot
access even with smc calls.
Change-Id: I588179b56ebc0c29200b55e6d61535fd3a7a3b7e
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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| 7b8fe2de | 25-Jan-2020 |
Andre Przywara <andre.przywara@arm.com> |
spe: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data struct
spe: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I75dbfafb67849833b3f7b5047e237651e3f553cd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| 5d52aea8 | 26-Jun-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: handler to check support for System Suspend
Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the
Tegra: handler to check support for System Suspend
Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".
This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".
Original change by: kalyani chidambaram <kalyanic@nvidia.com>
Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 6f47acdb | 20-Jun-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: platform handler to relocate BL32 image
This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZD
Tegra: platform handler to relocate BL32 image
This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.
Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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