| 24dd5a7b | 22-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add reboot function for PSCI
Add system_reset function in PSCI operations.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-
feat(plat/mediatek/mt8186): add reboot function for PSCI
Add system_reset function in PSCI operations.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I41001484f6244bd6ae7dedcfb6ce71cd6c035a1e
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| a68346a7 | 22-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8186): add power-off function for PSCI
Add support for system-off.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic734696aab
feat(plat/mdeiatek/mt8186): add power-off function for PSCI
Add support for system-off.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic734696aab1b71ae85bca6ed08e544a522ce5c95
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| 572f8adb | 25-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): apply erratas for MT8186
MT8186 uses Cortex A76 CPU, so we apply these erratas.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Ch
feat(plat/mediatek/mt8186): apply erratas for MT8186
MT8186 uses Cortex A76 CPU, so we apply these erratas.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84741535fbe429f664092f624c2da653532204cd
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| 06cb65ef | 14-Nov-2021 |
Garmin.Chang <Garmin.Chang@mediatek.com> |
feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
TEST=build pass
BUG=b:202871018
Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f
feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
TEST=build pass
BUG=b:202871018
Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f748
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
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| 1da57e54 | 08-Nov-2021 |
Garmin.Chang <Garmin.Chang@mediatek.com> |
feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.
TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018
Change-Id: Ibd5423
feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.
TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018
Change-Id: Ibd5423b70b3ca3f91edaa48d7ca5bc094e751510
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
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| 6e5d76ba | 12-Nov-2021 |
Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add RTC drivers
Add RTC drivers for EOSC calibration.
TEST=build pass
BUG=b:202871018
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change
feat(plat/mediatek/mt8186): add RTC drivers
Add RTC drivers for EOSC calibration.
TEST=build pass
BUG=b:202871018
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ib48c07204c4a614072ba710c042794b59e8a902a
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| 0fe7ae9c | 09-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.
This patch extends the MMU region 0 size to cover all mt8186 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I520c51338578bd68756cd02603ce6783f93daf51
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| 95ea87ff | 01-Nov-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable M
feat(plat/mediatek/mt8186): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.
TEST=build pass
BUG=b:202871018
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Idc669364c89cde0974d2940bd12987ee833d1965
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| af5a0c40 | 15-Oct-2021 |
Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b
feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b9c1c60a91c74c7d3f45c78a9403544373fa90f
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| 109b91e3 | 12-Oct-2021 |
Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.
TEST=build pass
BUG=b:202871018
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib
feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.
TEST=build pass
BUG=b:202871018
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib8a1c4e995288bf5f7981ea65f27727715fe5787
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| 206f125c | 11-Oct-2021 |
Christine Zhu <christine.zhu@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d02
feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d029983c7ce48fa116fafa7fa78c65349308014
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| 5aab27dc | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add SiP service
Add the basic SiP service.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4dcc7383237bb6c1f2494920cde
feat(plat/mediatek/mt8186): add SiP service
Add the basic SiP service.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4dcc7383237bb6c1f2494920cde21197754f6367
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| 5bc88ec6 | 06-Oct-2021 |
James Lo <james.lo@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jame
feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.
TEST=build pass
BUG=b:202871018
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I3bc90460a6a55dff8d3293e04482abcad789bbb2
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| d73e15e6 | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize delay_timer
Initialize delay_timer for delay functions.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib8f
feat(plat/mediatek/mt8186): initialize delay_timer
Initialize delay_timer for delay functions.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib8f52d1c674537795cc478015c83cca0f872df60
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| a6a0af57 | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d0944
feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d094410d178e4203e3a9294b851a30ba150
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| 1b17e34c | 03-Oct-2021 |
Penny Jan <penny.jan@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and w
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and will add more settings for
EMI MPU in next patch.
TEST=build pass
BUG=b:202871018
Signed-off-by: Penny Jan <penny.jan@mediatek.corp-partner.google.com>
Change-Id: Ia9e5030164e40e060a05e8f91d2ac88258c2e98e
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| ab453050 | 09-Dec-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.com> |
feat(plat/mediatek/mt8195): improve SPM wakeup log
To enhance debug efficiency, modify wakeup log:
1. Redefine strings of wakeup reason for readability.
2. Indicate 26M clock on/off state of previou
feat(plat/mediatek/mt8195): improve SPM wakeup log
To enhance debug efficiency, modify wakeup log:
1. Redefine strings of wakeup reason for readability.
2. Indicate 26M clock on/off state of previous suspend.
3. Add warning log if SPM cannot get wakeup reason.
BUG=b:205201535
TEST=build pass
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Icb14ebb08958da225969abd3cdd9e471d232c7eb
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| 690cb126 | 15-Nov-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.
BUG=b:20
feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.
BUG=b:204347737
TEST=build pass
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I7c9f8490b8898008ba6844c34c9e80caa6066cbc
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| 20ef588e | 15-Nov-2021 |
Tinghan Shen <tinghan.shen@mediatek.com> |
feat(plat/mediatek/mt8195): dump EMI MPU configurations
Add dump_emi_mpu_regions() to dump EMI MPU configurations.
BUG=b:204347737
TEST=build pass
Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1
feat(plat/mediatek/mt8195): dump EMI MPU configurations
Add dump_emi_mpu_regions() to dump EMI MPU configurations.
BUG=b:204347737
TEST=build pass
Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1b8f
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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| 27132f13 | 28-Sep-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
TEST=bu
feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id3e2f46a8c3ab2f3e29137e508d4c671e8f4aad5
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| 296b5902 | 08-Nov-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Ke
feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Kernel space.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
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| 88906b44 | 01-Nov-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
Add APU SiP call support for start/stop mcu.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I3bec0b588a2884327ba645e95
feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
Add APU SiP call support for start/stop mcu.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I3bec0b588a2884327ba645e9568c0150436afa42
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| 339e4924 | 01-Nov-2021 |
Flora Fu <flora.fu@mediatek.com> |
feat(plat/mediatek/apu): add mt8195 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
clock/pll register ranges.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If24cf21
feat(plat/mediatek/apu): add mt8195 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
clock/pll register ranges.
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If24cf21318813babfc2c11f38891521c7106b58c
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| 964ee4e6 | 11-Nov-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(mt8195): use correct print format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit variables.
Change-Id: I09a8d
fix(mt8195): use correct print format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit variables.
Change-Id: I09a8d174694d4b170a6ef2e4a03df13adc829c00
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| c260b324 | 13-Oct-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8195): remove adsp event from wakeup source
Audio DSP is power-off when system suspend. Remove it from
wakeup source list to prevent unnecessary wakeup.
Signed-off-by: Edward-J
feat(plat/mdeiatek/mt8195): remove adsp event from wakeup source
Audio DSP is power-off when system suspend. Remove it from
wakeup source list to prevent unnecessary wakeup.
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Id7251de9c8b9c9a4a4b2c41a310168d336035b9a
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