1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/console.h> 9 #include <lib/mmio.h> 10 11 #include <mtk_apusys.h> 12 #include <plat/common/platform.h> 13 14 int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 15 uint32_t *ret1) 16 { 17 int32_t ret = 0L; 18 uint32_t request_ops; 19 20 request_ops = (uint32_t)x1; 21 22 switch (request_ops) { 23 case MTK_SIP_APU_START_MCU: 24 /* setup addr[33:32] in reviser */ 25 mmio_write_32(REVISER_SECUREFW_CTXT, 0U); 26 mmio_write_32(REVISER_USDRFW_CTXT, 0U); 27 28 /* setup secure sideband */ 29 mmio_write_32(AO_SEC_FW, 30 (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) | 31 (0U << SEC_FW_DOMAIN_SHIFT)); 32 33 /* setup boot address */ 34 mmio_write_32(AO_MD32_BOOT_CTRL, 0U); 35 36 /* setup pre-define region */ 37 mmio_write_32(AO_MD32_PRE_DEFINE, 38 (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) | 39 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) | 40 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) | 41 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G)); 42 43 /* release runstall */ 44 mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN); 45 46 INFO("[APUSYS] rev(0x%08x,0x%08x)\n", 47 mmio_read_32(REVISER_SECUREFW_CTXT), 48 mmio_read_32(REVISER_USDRFW_CTXT)); 49 INFO("[APUSYS] ao(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x)\n", 50 mmio_read_32(AO_SEC_FW), 51 mmio_read_32(AO_SEC_USR_FW), 52 mmio_read_32(AO_MD32_BOOT_CTRL), 53 mmio_read_32(AO_MD32_PRE_DEFINE), 54 mmio_read_32(AO_MD32_SYS_CTRL)); 55 break; 56 case MTK_SIP_APU_STOP_MCU: 57 /* hold runstall */ 58 mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL); 59 60 INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n", 61 mmio_read_32(AO_MD32_BOOT_CTRL), 62 mmio_read_32(AO_MD32_SYS_CTRL)); 63 break; 64 default: 65 ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops); 66 break; 67 } 68 69 return ret; 70 } 71