fix(intel): set BIT2 of system manager MPFE Interface Select

Set BIT2 of system manager MPFE Interface Select register to
access the EMIF_1.

Change-Id: I6bb2776e5320bde326c6bf97cb785389cad5fb90
Sig

fix(intel): set BIT2 of system manager MPFE Interface Select

Set BIT2 of system manager MPFE Interface Select register to
access the EMIF_1.

Change-Id: I6bb2776e5320bde326c6bf97cb785389cad5fb90
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): unexpected DDR reset type value observed on Agilex5

Redesign the reset type detection logic in the DDR driver.
Implement a more robust and comprehensive check that accurately
distinguish

fix(intel): unexpected DDR reset type value observed on Agilex5

Redesign the reset type detection logic in the DDR driver.
Implement a more robust and comprehensive check that accurately
distinguishes all possible DDR_RESET_TYPE values, including 0x4
and any future additions.

Change-Id: I8f1abdc8269b0de68733e5fcb3f12b4a5640770e
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): flush the mailbox response buffer in SiPSVC V3

In SiPSVC V3, the user suppiled buffer will be directly used
for collecting the response from SDM mailbox - this way we
can avoid keeping t

fix(intel): flush the mailbox response buffer in SiPSVC V3

In SiPSVC V3, the user suppiled buffer will be directly used
for collecting the response from SDM mailbox - this way we
can avoid keeping the response local copy in the TF-A and
improve performance. Once the response is collected in the
user buffer, we need to FLUSH to maintain coherency.

Change-Id: I265ce177fe42d7ab647c875d52286de4b998672d
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update the RSU version logic read

Update the RSU version logic read, keep the version
with backward compatible as SiPSVC V1.

Change-Id: Ibb0f3bb631c7759e65ac028a9e52006f2f057e6f
Signed-

fix(intel): update the RSU version logic read

Update the RSU version logic read, keep the version
with backward compatible as SiPSVC V1.

Change-Id: Ibb0f3bb631c7759e65ac028a9e52006f2f057e6f
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update generic mailbox command filter method

Update generic mailbox command filter method, filter the
commands based on the mailbox spec command ID and not on
the SMC function ID.

Chang

fix(intel): update generic mailbox command filter method

Update generic mailbox command filter method, filter the
commands based on the mailbox spec command ID and not on
the SMC function ID.

Change-Id: Icceecc4c41858254d1a44e83552561f0b7c313ac
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): solve agilex warm reset issue" into integration

Merge "fix(intel): support DDR In-line and Out-of-Band ECC handling" into integration

Merge "feat(intel): move common functions to common lib files" into integration

Merge "fix(intel): add 5us delay before Linux reconfig to avoid HNOC hang" into integration

fix(intel): solve agilex warm reset issue

Agilex warm reset not able to trigger due to the system not able to
detect the magic number. ATF only able to solve for boot core.
For secondary cores, Linu

fix(intel): solve agilex warm reset issue

Agilex warm reset not able to trigger due to the system not able to
detect the magic number. ATF only able to solve for boot core.
For secondary cores, Linux need to update psci driver to WFI
the cores in EL3. Original Linux WFI is EL1.
Thus causing secondary cores not working

Change-Id: I5470abc19a09e45f16c4cd0049dd20e6534435bb
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): support DDR In-line and Out-of-Band ECC handling

Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the s

fix(intel): support DDR In-line and Out-of-Band ECC handling

Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the system accordingly.

Change-Id: I5138124e0d68dc8c93c98ae71eb13a77e49fd682
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): move common functions to common lib files

This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share a

feat(intel): move common functions to common lib files

This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share among files.

Change-Id: I19d9727eac895e7bf597a66076a7b68755cbe0ef
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): add 5us delay before Linux reconfig to avoid HNOC hang

On FP82, performing FPGA configuration in U-Boot followed by a
second configuration in Linux via devicetree overlay can lead
to a s

fix(intel): add 5us delay before Linux reconfig to avoid HNOC hang

On FP82, performing FPGA configuration in U-Boot followed by a
second configuration in Linux via devicetree overlay can lead
to a system hang. This issue does not occur on Agilex or Agilex5.

Root cause is tied to FP82's HNOC (Hardened Network-on-Chip),
which requires a brief settling period after bridge enablement
and initial fabric reconfiguration. Without this delay, HNOC
may still be transitioning, resulting in unstable FPGA access.

A 5us delay is added before the Linux reconfiguration step
to ensure HNOC is fully stabilized. Verified on FP82. No impact
on other platforms.

Change-Id: I083d395d34c797c4bf0a7e8aadc7c8866661fc15
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): update TFA to patch for Linux 6.12 rebase warning message" into integration

Merge "fix(intel): solve s10 warm reset issue" into integration

Merge changes I1bb556a8,Ie450acf7 into integration

* changes:
fix(intel): remove wfi polling when performing cpu on
fix(intel): fix socfpga_psci for cpu on off function

fix(intel): solve s10 warm reset issue

This is extension of the patch to fix the warm
reset issue in agilex refer to this commit 7f4fa931a.

The warm reset not able to trigger due to the system
not

fix(intel): solve s10 warm reset issue

This is extension of the patch to fix the warm
reset issue in agilex refer to this commit 7f4fa931a.

The warm reset not able to trigger due to the system
not able to detect the magic number. ATF only able
to solve for boot core. For secondary cores, Linux
need to update psci driver to WFI the cores in EL3.
Original Linux WFI is EL1.
Thus causing secondary cores not working.

Change-Id: Iee5e3f6d3334832fe432721fcf7b872534334988
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>

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fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will ca

fix(intel): remove wfi polling when performing cpu on

Polling the WFI status produces vague result as
the secondary CPU will keep changing it's states.

Removing the polling WFI code as this will cause
polling timeout since the CPU state is uncertain.

The CPU ON function will still work by removing this
check.

Change-Id: I1bb556a83ca16e122dfa35343de3e7cc39c5b678
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.

fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): configure usb3 system manager reg in TFA

Reset pulse override bit needs to be set for successful
reset staggering pulse generation.

The bit one of power over-current field actually refl

fix(intel): configure usb3 system manager reg in TFA

Reset pulse override bit needs to be set for successful
reset staggering pulse generation.

The bit one of power over-current field actually reflects
PIPE power present signal. This bit needs to be set to
avoid providing false information about VBus to the
HPS controller.

Change-Id: I123e2ec7c8ceaa15f47f90460fae5a325741dd10
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update TFA to patch for Linux 6.12 rebase warning message

On MMU-500 r2p0+ (used in newer SoCFPGA platforms),
we need to clear the SMMU_sACR.CACHE_LOCK bit
so the normal world can write

fix(intel): update TFA to patch for Linux 6.12 rebase warning message

On MMU-500 r2p0+ (used in newer SoCFPGA platforms),
we need to clear the SMMU_sACR.CACHE_LOCK bit
so the normal world can write to SMMU_CBn_ACTLR.

Change-Id: I0d0d227950508a2969fe0fe2eddbe6894efe54bc
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix variable may be used uninitialized error

When building with LTO, the compiler can correctly see that there are
code paths that can lead to a variable used without it being written to

fix(intel): fix variable may be used uninitialized error

When building with LTO, the compiler can correctly see that there are
code paths that can lead to a variable used without it being written to.
Give these variables a starting value of 0 as a reasonable default
if/when this happens and to make the compiler happy.

Change-Id: I1d1efdbc59945d15a18fb3cfd498061eb681e5f9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I3303ca9a,I682da2d3 into integration

* changes:
feat(intel): migrate RSU client to SiPSVC V3
fix(intel): support generic mailbox command in SiPSVC V3

Merge "fix(intel): support SMC 64bit return args in SiPSVC V3" into integration

Merge changes I23e51bf9,I0fa9adaf into integration

* changes:
fix(intel): verify data size in AES GCM and GCM-GHASH modes
fix(intel): update FCS AES method for GCM block modes