1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <tools_share/uuid.h> 15 16 #include "socfpga_fcs.h" 17 #include "socfpga_mailbox.h" 18 #include "socfpga_plat_def.h" 19 #include "socfpga_reset_manager.h" 20 #include "socfpga_sip_svc.h" 21 #include "socfpga_system_manager.h" 22 23 /* Total buffer the driver can hold */ 24 #define FPGA_CONFIG_BUFFER_SIZE 4 25 26 static config_type request_type = NO_REQUEST; 27 static int current_block, current_buffer; 28 static int read_block, max_blocks; 29 static uint32_t send_id, rcv_id; 30 static uint32_t bytes_per_block, blocks_submitted; 31 static bool bridge_disable; 32 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 33 static uint32_t g_remapper_bypass; 34 #endif 35 36 /* RSU static variables */ 37 static uint32_t rsu_dcmf_ver[4] = {0}; 38 static uint16_t rsu_dcmf_stat[4] = {0}; 39 static uint32_t rsu_max_retry; 40 41 /* SiP Service UUID */ 42 DEFINE_SVC_UUID2(intl_svc_uid, 43 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 44 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 45 46 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 47 uint64_t x1, 48 uint64_t x2, 49 uint64_t x3, 50 uint64_t x4, 51 void *cookie, 52 void *handle, 53 uint64_t flags) 54 { 55 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 56 SMC_RET1(handle, SMC_UNK); 57 } 58 59 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 60 61 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 62 { 63 uint32_t args[3]; 64 65 while (max_blocks > 0 && buffer->size > buffer->size_written) { 66 args[0] = (1<<8); 67 args[1] = buffer->addr + buffer->size_written; 68 if (buffer->size - buffer->size_written <= bytes_per_block) { 69 args[2] = buffer->size - buffer->size_written; 70 current_buffer++; 71 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 72 } else { 73 args[2] = bytes_per_block; 74 } 75 76 buffer->size_written += args[2]; 77 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 78 3U, CMD_INDIRECT); 79 80 buffer->subblocks_sent++; 81 max_blocks--; 82 } 83 84 return !max_blocks; 85 } 86 87 static int intel_fpga_sdm_write_all(void) 88 { 89 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 90 if (intel_fpga_sdm_write_buffer( 91 &fpga_config_buffers[current_buffer])) { 92 break; 93 } 94 } 95 return 0; 96 } 97 98 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 99 { 100 uint32_t ret; 101 102 if (err_states == NULL) 103 return INTEL_SIP_SMC_STATUS_REJECTED; 104 105 switch (request_type) { 106 case RECONFIGURATION: 107 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 108 true, err_states); 109 break; 110 case BITSTREAM_AUTH: 111 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 112 false, err_states); 113 break; 114 default: 115 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 116 false, err_states); 117 break; 118 } 119 120 if (ret != 0U) { 121 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 122 return INTEL_SIP_SMC_STATUS_BUSY; 123 } else { 124 request_type = NO_REQUEST; 125 return INTEL_SIP_SMC_STATUS_ERROR; 126 } 127 } 128 129 if (bridge_disable != 0U) { 130 socfpga_bridges_enable(~0); /* Enable bridge */ 131 bridge_disable = false; 132 } 133 request_type = NO_REQUEST; 134 135 return INTEL_SIP_SMC_STATUS_OK; 136 } 137 138 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 139 { 140 int i; 141 142 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 143 if (fpga_config_buffers[i].block_number == current_block) { 144 fpga_config_buffers[i].subblocks_sent--; 145 if (fpga_config_buffers[i].subblocks_sent == 0 146 && fpga_config_buffers[i].size <= 147 fpga_config_buffers[i].size_written) { 148 fpga_config_buffers[i].write_requested = 0; 149 current_block++; 150 *buffer_addr_completed = 151 fpga_config_buffers[i].addr; 152 return 0; 153 } 154 } 155 } 156 157 return -1; 158 } 159 160 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 161 uint32_t *count, uint32_t *job_id) 162 { 163 uint32_t resp[5]; 164 unsigned int resp_len = ARRAY_SIZE(resp); 165 int status = INTEL_SIP_SMC_STATUS_OK; 166 int all_completed = 1; 167 *count = 0; 168 169 while (*count < 3) { 170 171 status = mailbox_read_response(job_id, 172 resp, &resp_len); 173 174 if (status < 0) { 175 break; 176 } 177 178 max_blocks++; 179 180 if (mark_last_buffer_xfer_completed( 181 &completed_addr[*count]) == 0) { 182 *count = *count + 1; 183 } else { 184 break; 185 } 186 } 187 188 if (*count <= 0) { 189 if (status != MBOX_NO_RESPONSE && 190 status != MBOX_TIMEOUT && resp_len != 0) { 191 mailbox_clear_response(); 192 request_type = NO_REQUEST; 193 return INTEL_SIP_SMC_STATUS_ERROR; 194 } 195 196 *count = 0; 197 } 198 199 intel_fpga_sdm_write_all(); 200 201 if (*count > 0) { 202 status = INTEL_SIP_SMC_STATUS_OK; 203 } else if (*count == 0) { 204 status = INTEL_SIP_SMC_STATUS_BUSY; 205 } 206 207 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 208 if (fpga_config_buffers[i].write_requested != 0) { 209 all_completed = 0; 210 break; 211 } 212 } 213 214 if (all_completed == 1) { 215 return INTEL_SIP_SMC_STATUS_OK; 216 } 217 218 return status; 219 } 220 221 static int intel_fpga_config_start(uint32_t flag) 222 { 223 uint32_t argument = 0x1; 224 uint32_t response[3]; 225 int status = 0; 226 unsigned int size = 0; 227 unsigned int resp_len = ARRAY_SIZE(response); 228 229 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 230 /* 231 * To trigger isolation 232 * FPGA configuration complete signal should be de-asserted 233 */ 234 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 235 status = mailbox_send_fpga_config_comp(); 236 237 if (status < 0) { 238 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 239 } 240 #endif 241 242 request_type = RECONFIGURATION; 243 244 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 245 bridge_disable = true; 246 } 247 248 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 249 size = 1; 250 bridge_disable = false; 251 request_type = BITSTREAM_AUTH; 252 } 253 254 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 255 intel_smmu_hps_remapper_init(0U); 256 #endif 257 258 mailbox_clear_response(); 259 260 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 261 CMD_CASUAL, NULL, NULL); 262 263 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 264 CMD_CASUAL, response, &resp_len); 265 266 if (status < 0) { 267 bridge_disable = false; 268 request_type = NO_REQUEST; 269 return INTEL_SIP_SMC_STATUS_ERROR; 270 } 271 272 max_blocks = response[0]; 273 bytes_per_block = response[1]; 274 275 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 276 fpga_config_buffers[i].size = 0; 277 fpga_config_buffers[i].size_written = 0; 278 fpga_config_buffers[i].addr = 0; 279 fpga_config_buffers[i].write_requested = 0; 280 fpga_config_buffers[i].block_number = 0; 281 fpga_config_buffers[i].subblocks_sent = 0; 282 } 283 284 blocks_submitted = 0; 285 current_block = 0; 286 read_block = 0; 287 current_buffer = 0; 288 289 /* Disable bridge on full reconfiguration */ 290 if (bridge_disable) { 291 socfpga_bridges_disable(~0); 292 } 293 294 return INTEL_SIP_SMC_STATUS_OK; 295 } 296 297 static bool is_fpga_config_buffer_full(void) 298 { 299 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 300 if (!fpga_config_buffers[i].write_requested) { 301 return false; 302 } 303 } 304 return true; 305 } 306 307 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 308 { 309 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 310 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 311 312 if (!addr && !size) { 313 return true; 314 } 315 if (size > (UINT64_MAX - addr)) { 316 return false; 317 } 318 if (addr < BL31_LIMIT) { 319 return false; 320 } 321 if (dram_region_end > dram_max_sz) { 322 return false; 323 } 324 325 return true; 326 } 327 328 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 329 { 330 int i; 331 332 intel_fpga_sdm_write_all(); 333 334 if (!is_address_in_ddr_range(mem, size) || 335 is_fpga_config_buffer_full()) { 336 return INTEL_SIP_SMC_STATUS_REJECTED; 337 } 338 339 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 340 intel_smmu_hps_remapper_init(&mem); 341 #endif 342 343 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 344 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 345 346 if (!fpga_config_buffers[j].write_requested) { 347 fpga_config_buffers[j].addr = mem; 348 fpga_config_buffers[j].size = size; 349 fpga_config_buffers[j].size_written = 0; 350 fpga_config_buffers[j].write_requested = 1; 351 fpga_config_buffers[j].block_number = 352 blocks_submitted++; 353 fpga_config_buffers[j].subblocks_sent = 0; 354 break; 355 } 356 } 357 358 if (is_fpga_config_buffer_full()) { 359 return INTEL_SIP_SMC_STATUS_BUSY; 360 } 361 362 return INTEL_SIP_SMC_STATUS_OK; 363 } 364 365 static int is_out_of_sec_range(uint64_t reg_addr) 366 { 367 #if DEBUG 368 return 0; 369 #endif 370 371 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 372 switch (reg_addr) { 373 case(0xF8011100): /* ECCCTRL1 */ 374 case(0xF8011104): /* ECCCTRL2 */ 375 case(0xF8011110): /* ERRINTEN */ 376 case(0xF8011114): /* ERRINTENS */ 377 case(0xF8011118): /* ERRINTENR */ 378 case(0xF801111C): /* INTMODE */ 379 case(0xF8011120): /* INTSTAT */ 380 case(0xF8011124): /* DIAGINTTEST */ 381 case(0xF801112C): /* DERRADDRA */ 382 case(0xFA000000): /* SMMU SCR0 */ 383 case(0xFA000004): /* SMMU SCR1 */ 384 case(0xFA000400): /* SMMU NSCR0 */ 385 case(0xFA004000): /* SMMU SSD0_REG */ 386 case(0xFA000820): /* SMMU SMR8 */ 387 case(0xFA000c20): /* SMMU SCR8 */ 388 case(0xFA028000): /* SMMU CB8_SCTRL */ 389 case(0xFA001020): /* SMMU CBAR8 */ 390 case(0xFA028030): /* SMMU TCR_LPAE */ 391 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 392 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 393 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 394 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 395 case(0xFA028010): /* SMMU_CB8)TCR2 */ 396 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 397 case(0xFA001820): /* SMMU_CBA2R8 */ 398 case(0xFA000074): /* SMMU_STLBGSTATUS */ 399 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 400 case(0xFA000060): /* SMMU_STLBIALL */ 401 case(0xFA000070): /* SMMU_STLBGSYNC */ 402 case(0xFA028618): /* CB8_TLBALL */ 403 case(0xFA0287F0): /* CB8_TLBSYNC */ 404 case(0xFFD12028): /* SDMMCGRP_CTRL */ 405 case(0xFFD12044): /* EMAC0 */ 406 case(0xFFD12048): /* EMAC1 */ 407 case(0xFFD1204C): /* EMAC2 */ 408 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 409 case(0xFFD12094): /* ECC_INT_MASK_SET */ 410 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 411 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 412 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 413 case(0xFFD120C0): /* NOC_TIMEOUT */ 414 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 415 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 416 case(0xFFD120D0): /* NOC_IDLEACK */ 417 case(0xFFD120D4): /* NOC_IDLESTATUS */ 418 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 419 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 420 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 421 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 422 return 0; 423 #else 424 switch (reg_addr) { 425 426 case(0xF8011104): /* ECCCTRL2 */ 427 case(0xFFD12028): /* SDMMCGRP_CTRL */ 428 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 429 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 430 case(0xFFD120D0): /* NOC_IDLEACK */ 431 432 433 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 434 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 435 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 436 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 437 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 438 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 439 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 440 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 441 442 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 443 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 444 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 445 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 446 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 450 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 451 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 452 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 453 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 456 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 457 #endif 458 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 459 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 460 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 461 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 462 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 463 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 464 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 465 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 466 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 467 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 468 return 0; 469 470 default: 471 break; 472 } 473 474 return -1; 475 } 476 477 /* Secure register access */ 478 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 479 { 480 if (is_out_of_sec_range(reg_addr)) { 481 return INTEL_SIP_SMC_STATUS_ERROR; 482 } 483 484 *retval = mmio_read_32(reg_addr); 485 486 return INTEL_SIP_SMC_STATUS_OK; 487 } 488 489 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 490 uint32_t *retval) 491 { 492 if (is_out_of_sec_range(reg_addr)) { 493 return INTEL_SIP_SMC_STATUS_ERROR; 494 } 495 496 switch (reg_addr) { 497 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 498 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 499 mmio_write_16(reg_addr, val); 500 break; 501 default: 502 mmio_write_32(reg_addr, val); 503 break; 504 } 505 506 return intel_secure_reg_read(reg_addr, retval); 507 } 508 509 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 510 uint32_t val, uint32_t *retval) 511 { 512 if (!intel_secure_reg_read(reg_addr, retval)) { 513 *retval &= ~mask; 514 *retval |= val & mask; 515 return intel_secure_reg_write(reg_addr, *retval, retval); 516 } 517 518 return INTEL_SIP_SMC_STATUS_ERROR; 519 } 520 521 /* Intel Remote System Update (RSU) services */ 522 uint64_t intel_rsu_update_address; 523 524 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 525 { 526 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 527 return INTEL_SIP_SMC_RSU_ERROR; 528 } 529 530 return INTEL_SIP_SMC_STATUS_OK; 531 } 532 533 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 534 unsigned int respbuf_sz) 535 { 536 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 537 return INTEL_SIP_SMC_RSU_ERROR; 538 } 539 540 return INTEL_SIP_SMC_STATUS_OK; 541 } 542 543 uint32_t intel_rsu_update(uint64_t update_address) 544 { 545 if (update_address > SIZE_MAX) { 546 return INTEL_SIP_SMC_STATUS_REJECTED; 547 } 548 549 intel_rsu_update_address = update_address; 550 return INTEL_SIP_SMC_STATUS_OK; 551 } 552 553 static uint32_t intel_rsu_notify(uint32_t execution_stage) 554 { 555 if (mailbox_hps_stage_notify(execution_stage) < 0) { 556 return INTEL_SIP_SMC_RSU_ERROR; 557 } 558 559 return INTEL_SIP_SMC_STATUS_OK; 560 } 561 562 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 563 uint32_t *ret_stat) 564 { 565 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 566 return INTEL_SIP_SMC_RSU_ERROR; 567 } 568 569 *ret_stat = respbuf[8]; 570 return INTEL_SIP_SMC_STATUS_OK; 571 } 572 573 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 574 uint64_t dcmf_ver_3_2) 575 { 576 rsu_dcmf_ver[0] = dcmf_ver_1_0; 577 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 578 rsu_dcmf_ver[2] = dcmf_ver_3_2; 579 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 580 581 return INTEL_SIP_SMC_STATUS_OK; 582 } 583 584 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 585 { 586 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 587 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 588 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 589 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 590 591 return INTEL_SIP_SMC_STATUS_OK; 592 } 593 594 /* Intel HWMON services */ 595 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 596 { 597 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 598 return INTEL_SIP_SMC_STATUS_ERROR; 599 } 600 601 return INTEL_SIP_SMC_STATUS_OK; 602 } 603 604 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 605 { 606 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 607 return INTEL_SIP_SMC_STATUS_ERROR; 608 } 609 610 return INTEL_SIP_SMC_STATUS_OK; 611 } 612 613 /* Mailbox services */ 614 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 615 { 616 int status; 617 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 618 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 619 620 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 621 CMD_CASUAL, resp_data, &resp_len); 622 623 if (status < 0) { 624 return INTEL_SIP_SMC_STATUS_ERROR; 625 } 626 627 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 628 return INTEL_SIP_SMC_STATUS_ERROR; 629 } 630 631 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 632 633 return INTEL_SIP_SMC_STATUS_OK; 634 } 635 636 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 637 unsigned int len, uint32_t urgent, uint64_t response, 638 unsigned int resp_len, int *mbox_status, 639 unsigned int *len_in_resp) 640 { 641 *len_in_resp = 0; 642 *mbox_status = GENERIC_RESPONSE_ERROR; 643 644 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 645 return INTEL_SIP_SMC_STATUS_REJECTED; 646 } 647 648 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 649 (uint32_t *) response, &resp_len); 650 651 if (status < 0) { 652 *mbox_status = -status; 653 return INTEL_SIP_SMC_STATUS_ERROR; 654 } 655 656 *mbox_status = 0; 657 *len_in_resp = resp_len; 658 659 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 660 661 return INTEL_SIP_SMC_STATUS_OK; 662 } 663 664 static int intel_smc_get_usercode(uint32_t *user_code) 665 { 666 int status; 667 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 668 669 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 670 0U, CMD_CASUAL, user_code, &resp_len); 671 672 if (status < 0) { 673 return INTEL_SIP_SMC_STATUS_ERROR; 674 } 675 676 return INTEL_SIP_SMC_STATUS_OK; 677 } 678 679 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 680 uint32_t mode, uint32_t *job_id, 681 uint32_t *ret_size, uint32_t *mbox_error) 682 { 683 int status = 0; 684 uint32_t resp_len = size / MBOX_WORD_BYTE; 685 686 if (resp_len > MBOX_DATA_MAX_LEN) { 687 return INTEL_SIP_SMC_STATUS_REJECTED; 688 } 689 690 if (!is_address_in_ddr_range(addr, size)) { 691 return INTEL_SIP_SMC_STATUS_REJECTED; 692 } 693 694 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 695 status = mailbox_read_response_async(job_id, 696 NULL, (uint32_t *) addr, &resp_len, 0); 697 } else { 698 status = mailbox_read_response(job_id, 699 (uint32_t *) addr, &resp_len); 700 701 if (status == MBOX_NO_RESPONSE) { 702 status = MBOX_BUSY; 703 } 704 } 705 706 if (status == MBOX_NO_RESPONSE) { 707 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 708 } 709 710 if (status == MBOX_BUSY) { 711 return INTEL_SIP_SMC_STATUS_BUSY; 712 } 713 714 *ret_size = resp_len * MBOX_WORD_BYTE; 715 flush_dcache_range(addr, *ret_size); 716 717 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 718 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 719 *mbox_error = -status; 720 } else if (status != MBOX_RET_OK) { 721 *mbox_error = -status; 722 return INTEL_SIP_SMC_STATUS_ERROR; 723 } 724 725 return INTEL_SIP_SMC_STATUS_OK; 726 } 727 728 /* Miscellaneous HPS services */ 729 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 730 { 731 int status = 0; 732 733 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 734 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 735 status = socfpga_bridges_enable((uint32_t)mask); 736 } else { 737 status = socfpga_bridges_enable(~0); 738 } 739 } else { 740 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 741 status = socfpga_bridges_disable((uint32_t)mask); 742 } else { 743 status = socfpga_bridges_disable(~0); 744 } 745 } 746 747 if (status < 0) { 748 return INTEL_SIP_SMC_STATUS_ERROR; 749 } 750 751 return INTEL_SIP_SMC_STATUS_OK; 752 } 753 754 /* SDM SEU Error services */ 755 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 756 { 757 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 758 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 759 } 760 761 return INTEL_SIP_SMC_STATUS_OK; 762 } 763 764 /* SDM SAFE SEU Error inject services */ 765 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 766 { 767 if (mailbox_safe_inject_seu_err(command, len) < 0) { 768 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 769 } 770 771 return INTEL_SIP_SMC_STATUS_OK; 772 } 773 774 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 775 /* SMMU HPS Remapper */ 776 void intel_smmu_hps_remapper_init(uint64_t *mem) 777 { 778 /* Read out Bit 1 value */ 779 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 780 781 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 782 /* Update DRAM Base address for SDM SMMU */ 783 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 784 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 785 *mem = *mem - DRAM_BASE; 786 } else { 787 *mem = *mem - DRAM_BASE; 788 } 789 } 790 791 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 792 { 793 /* Read out the JTAG-ID from boot scratch register */ 794 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 795 if (remapper_bypass == 0x01) { 796 g_remapper_bypass = remapper_bypass; 797 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 798 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 799 } 800 } 801 return INTEL_SIP_SMC_STATUS_OK; 802 } 803 804 static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command) 805 { 806 volatile uint64_t atf_ddr_buffer; 807 volatile uint64_t val; 808 809 mmio_write_32(IOSSM_CMD_PARAM, *syndrome); 810 mmio_write_32(IOSSM_CMD_TRIG_OP, command); 811 udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS); 812 atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */ 813 memcpy_s((void *)&val, sizeof(val), 814 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer)); 815 816 /* Clear response_ready BIT0 of status_register before sending next command. */ 817 mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY); 818 } 819 #endif 820 821 #if SIP_SVC_V3 822 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint32_t *ret_args) 823 { 824 uint8_t ret_args_len = 0U; 825 sdm_response_t *resp = (sdm_response_t *)resp_desc; 826 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 827 828 (void)cmd; 829 /* Returns 3 SMC arguments for SMC_RET3 */ 830 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 831 ret_args[ret_args_len++] = resp->err_code; 832 833 return ret_args_len; 834 } 835 836 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint32_t *ret_args) 837 { 838 uint8_t ret_args_len = 0U; 839 sdm_response_t *resp = (sdm_response_t *)resp_desc; 840 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 841 842 (void)cmd; 843 /* Returns 3 SMC arguments for SMC_RET3 */ 844 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 845 ret_args[ret_args_len++] = resp->err_code; 846 ret_args[ret_args_len++] = resp->resp_data[0]; 847 848 return ret_args_len; 849 } 850 851 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args) 852 { 853 uint8_t ret_args_len = 0U; 854 sdm_response_t *resp = (sdm_response_t *)resp_desc; 855 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 856 857 (void)cmd; 858 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 859 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 860 861 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 862 ret_args[ret_args_len++] = resp->err_code; 863 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 864 865 return ret_args_len; 866 } 867 868 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args) 869 { 870 uint8_t ret_args_len = 0U; 871 sdm_response_t *resp = (sdm_response_t *)resp_desc; 872 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 873 874 (void)cmd; 875 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 876 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 877 878 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 879 ret_args[ret_args_len++] = resp->err_code; 880 ret_args[ret_args_len++] = resp->resp_data[0]; 881 ret_args[ret_args_len++] = resp->resp_data[1]; 882 883 return ret_args_len; 884 } 885 886 static uintptr_t smc_ret(void *handle, uint32_t *ret_args, uint32_t ret_args_len) 887 { 888 switch (ret_args_len) { 889 case SMC_RET_ARGS_ONE: 890 SMC_RET1(handle, ret_args[0]); 891 break; 892 893 case SMC_RET_ARGS_TWO: 894 SMC_RET2(handle, ret_args[0], ret_args[1]); 895 break; 896 897 case SMC_RET_ARGS_THREE: 898 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 899 break; 900 901 case SMC_RET_ARGS_FOUR: 902 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 903 break; 904 905 case SMC_RET_ARGS_FIVE: 906 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 907 break; 908 909 default: 910 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 911 break; 912 } 913 } 914 915 /* 916 * This function is responsible for handling all SiP SVC V3 calls from the 917 * non-secure world. 918 */ 919 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 920 u_register_t x1, 921 u_register_t x2, 922 u_register_t x3, 923 u_register_t x4, 924 void *cookie, 925 void *handle, 926 u_register_t flags) 927 { 928 int status = 0; 929 uint32_t mbox_error = 0U; 930 u_register_t x5, x6, x7, x8, x9, x10, x11; 931 932 /* Get all the SMC call arguments */ 933 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 934 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 935 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 936 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 937 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 938 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 939 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 940 941 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 942 smc_fid, x1, x2, x3, x4, x5); 943 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 944 x6, x7, x8, x9, x10, x11); 945 946 switch (smc_fid) { 947 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 948 { 949 uint32_t ret_args[8] = {0}; 950 uint32_t ret_args_len = 0; 951 952 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 953 GET_JOB_ID(x1), 954 ret_args, 955 &ret_args_len); 956 /* Always reserve [0] index for command status. */ 957 ret_args[0] = status; 958 959 /* Return SMC call based on the number of return arguments */ 960 return smc_ret(handle, ret_args, ret_args_len); 961 } 962 963 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 964 { 965 /* TBD: Here now we don't need these CID and JID?? */ 966 uint8_t client_id = 0U; 967 uint8_t job_id = 0U; 968 uint64_t trans_id_bitmap[4] = {0U}; 969 970 status = mailbox_response_poll_on_intr_v3(&client_id, 971 &job_id, 972 trans_id_bitmap); 973 974 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 975 trans_id_bitmap[2], trans_id_bitmap[3]); 976 break; 977 } 978 979 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 980 { 981 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 982 GET_JOB_ID(x1), 983 MBOX_CMD_GET_DEVICEID, 984 NULL, 985 0U, 986 MBOX_CMD_FLAG_CASUAL, 987 sip_smc_ret_nbytes_cb, 988 (uint32_t *)x2, 989 2); 990 991 SMC_RET1(handle, status); 992 } 993 994 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 995 { 996 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 997 GET_JOB_ID(x1), 998 MBOX_CMD_GET_IDCODE, 999 NULL, 1000 0U, 1001 MBOX_CMD_FLAG_CASUAL, 1002 sip_smc_cmd_cb_ret3, 1003 NULL, 1004 0); 1005 1006 SMC_RET1(handle, status); 1007 } 1008 1009 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1010 { 1011 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1012 GET_JOB_ID(x1), 1013 MBOX_CMD_QSPI_OPEN, 1014 NULL, 1015 0U, 1016 MBOX_CMD_FLAG_CASUAL, 1017 sip_smc_cmd_cb_ret2, 1018 NULL, 1019 0U); 1020 1021 SMC_RET1(handle, status); 1022 } 1023 1024 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1025 { 1026 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1027 GET_JOB_ID(x1), 1028 MBOX_CMD_QSPI_CLOSE, 1029 NULL, 1030 0U, 1031 MBOX_CMD_FLAG_CASUAL, 1032 sip_smc_cmd_cb_ret2, 1033 NULL, 1034 0U); 1035 1036 SMC_RET1(handle, status); 1037 } 1038 1039 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1040 { 1041 uint32_t cmd_data = 0U; 1042 uint32_t chip_sel = (uint32_t)x2; 1043 uint32_t comb_addr_mode = (uint32_t)x3; 1044 uint32_t ext_dec_mode = (uint32_t)x4; 1045 1046 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1047 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1048 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1049 1050 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1051 GET_JOB_ID(x1), 1052 MBOX_CMD_QSPI_SET_CS, 1053 &cmd_data, 1054 1U, 1055 MBOX_CMD_FLAG_CASUAL, 1056 sip_smc_cmd_cb_ret2, 1057 NULL, 1058 0U); 1059 1060 SMC_RET1(handle, status); 1061 } 1062 1063 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1064 { 1065 uint32_t qspi_addr = (uint32_t)x2; 1066 uint32_t qspi_nwords = (uint32_t)x3; 1067 1068 /* QSPI address offset to start erase, must be 4K aligned */ 1069 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1070 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1071 smc_fid); 1072 status = INTEL_SIP_SMC_STATUS_REJECTED; 1073 SMC_RET1(handle, status); 1074 } 1075 1076 /* Number of words to erase, multiples of 0x400 or 4K */ 1077 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1078 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1079 smc_fid); 1080 status = INTEL_SIP_SMC_STATUS_REJECTED; 1081 SMC_RET1(handle, status); 1082 } 1083 1084 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1085 1086 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1087 GET_JOB_ID(x1), 1088 MBOX_CMD_QSPI_ERASE, 1089 cmd_data, 1090 sizeof(cmd_data) / MBOX_WORD_BYTE, 1091 MBOX_CMD_FLAG_CASUAL, 1092 sip_smc_cmd_cb_ret2, 1093 NULL, 1094 0U); 1095 1096 SMC_RET1(handle, status); 1097 } 1098 1099 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1100 { 1101 uint32_t *qspi_payload = (uint32_t *)x2; 1102 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1103 uint32_t qspi_addr = qspi_payload[0]; 1104 uint32_t qspi_nwords = qspi_payload[1]; 1105 1106 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1107 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1108 smc_fid); 1109 status = INTEL_SIP_SMC_STATUS_REJECTED; 1110 SMC_RET1(handle, status); 1111 } 1112 1113 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1114 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1115 smc_fid); 1116 status = INTEL_SIP_SMC_STATUS_REJECTED; 1117 SMC_RET1(handle, status); 1118 } 1119 1120 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1121 GET_JOB_ID(x1), 1122 MBOX_CMD_QSPI_WRITE, 1123 qspi_payload, 1124 qspi_total_nwords, 1125 MBOX_CMD_FLAG_CASUAL, 1126 sip_smc_cmd_cb_ret2, 1127 NULL, 1128 0U); 1129 1130 SMC_RET1(handle, status); 1131 } 1132 1133 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1134 { 1135 uint32_t qspi_addr = (uint32_t)x2; 1136 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1137 1138 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1139 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1140 smc_fid); 1141 status = INTEL_SIP_SMC_STATUS_REJECTED; 1142 SMC_RET1(handle, status); 1143 } 1144 1145 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1146 1147 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1148 GET_JOB_ID(x1), 1149 MBOX_CMD_QSPI_READ, 1150 cmd_data, 1151 sizeof(cmd_data) / MBOX_WORD_BYTE, 1152 MBOX_CMD_FLAG_CASUAL, 1153 sip_smc_ret_nbytes_cb, 1154 (uint32_t *)x3, 1155 2); 1156 1157 SMC_RET1(handle, status); 1158 } 1159 1160 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1161 { 1162 uint32_t *dst_addr = (uint32_t *)x2; 1163 1164 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1165 GET_JOB_ID(x1), 1166 MBOX_CMD_QSPI_GET_DEV_INFO, 1167 NULL, 1168 0U, 1169 MBOX_CMD_FLAG_CASUAL, 1170 sip_smc_ret_nbytes_cb, 1171 (uint32_t *)dst_addr, 1172 2); 1173 1174 SMC_RET1(handle, status); 1175 } 1176 1177 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1178 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1179 { 1180 uint32_t channel = (uint32_t)x2; 1181 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1182 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1183 1184 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1185 GET_JOB_ID(x1), 1186 mbox_cmd, 1187 &channel, 1188 1U, 1189 MBOX_CMD_FLAG_CASUAL, 1190 sip_smc_cmd_cb_ret3, 1191 NULL, 1192 0); 1193 1194 SMC_RET1(handle, status); 1195 } 1196 1197 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1198 { 1199 uint32_t session_id = (uint32_t)x2; 1200 uint32_t context_id = (uint32_t)x3; 1201 uint64_t ret_random_addr = (uint64_t)x4; 1202 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1203 uint32_t crypto_header = 0U; 1204 1205 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1206 (random_len == 0U) || 1207 (!is_size_4_bytes_aligned(random_len))) { 1208 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1209 status = INTEL_SIP_SMC_STATUS_REJECTED; 1210 SMC_RET1(handle, status); 1211 } 1212 1213 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1214 FCS_CS_FIELD_FLAG_OFFSET); 1215 fcs_rng_payload payload = {session_id, context_id, 1216 crypto_header, random_len}; 1217 1218 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1219 GET_JOB_ID(x1), 1220 MBOX_FCS_RANDOM_GEN, 1221 (uint32_t *)&payload, 1222 sizeof(payload) / MBOX_WORD_BYTE, 1223 MBOX_CMD_FLAG_CASUAL, 1224 sip_smc_ret_nbytes_cb, 1225 (uint32_t *)ret_random_addr, 1226 2); 1227 SMC_RET1(handle, status); 1228 } 1229 1230 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1231 { 1232 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1233 GET_JOB_ID(x1), 1234 MBOX_FCS_GET_PROVISION, 1235 NULL, 1236 0U, 1237 MBOX_CMD_FLAG_CASUAL, 1238 sip_smc_ret_nbytes_cb, 1239 (uint32_t *)x2, 1240 2); 1241 SMC_RET1(handle, status); 1242 } 1243 1244 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1245 { 1246 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1247 x4, &mbox_error); 1248 SMC_RET1(handle, status); 1249 } 1250 1251 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1252 { 1253 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1254 GET_JOB_ID(x1), 1255 MBOX_CMD_GET_CHIPID, 1256 NULL, 1257 0U, 1258 MBOX_CMD_FLAG_CASUAL, 1259 sip_smc_get_chipid_cb, 1260 NULL, 1261 0); 1262 SMC_RET1(handle, status); 1263 } 1264 1265 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1266 { 1267 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1268 (uint32_t *) &x4, &mbox_error); 1269 SMC_RET1(handle, status); 1270 } 1271 1272 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1273 { 1274 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1275 x2, &mbox_error); 1276 SMC_RET1(handle, status); 1277 } 1278 1279 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1280 { 1281 if (x4 == FCS_MODE_ENCRYPT) { 1282 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1283 x5, x6, x7, (uint32_t *) &x8, 1284 &mbox_error, x10, x11); 1285 } else if (x4 == FCS_MODE_DECRYPT) { 1286 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1287 x5, x6, x7, (uint32_t *) &x8, 1288 &mbox_error, x9, x10, x11); 1289 } else { 1290 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1291 status = INTEL_SIP_SMC_STATUS_REJECTED; 1292 } 1293 SMC_RET1(handle, status); 1294 } 1295 1296 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1297 { 1298 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1299 SMC_RET1(handle, status); 1300 } 1301 1302 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1303 { 1304 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1305 GET_JOB_ID(x1), 1306 MBOX_FCS_OPEN_CS_SESSION, 1307 NULL, 1308 0U, 1309 MBOX_CMD_FLAG_CASUAL, 1310 sip_smc_cmd_cb_ret3, 1311 NULL, 1312 0); 1313 SMC_RET1(handle, status); 1314 } 1315 1316 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1317 { 1318 uint32_t session_id = (uint32_t)x2; 1319 1320 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1321 GET_JOB_ID(x1), 1322 MBOX_FCS_CLOSE_CS_SESSION, 1323 &session_id, 1324 1U, 1325 MBOX_CMD_FLAG_CASUAL, 1326 sip_smc_cmd_cb_ret2, 1327 NULL, 1328 0); 1329 SMC_RET1(handle, status); 1330 } 1331 1332 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1333 { 1334 uint64_t key_addr = x2; 1335 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1336 1337 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1338 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1339 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1340 smc_fid); 1341 status = INTEL_SIP_SMC_STATUS_REJECTED; 1342 SMC_RET1(handle, status); 1343 } 1344 1345 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1346 GET_JOB_ID(x1), 1347 MBOX_FCS_IMPORT_CS_KEY, 1348 (uint32_t *)key_addr, 1349 key_len_words, 1350 MBOX_CMD_FLAG_CASUAL, 1351 sip_smc_cmd_cb_ret3, 1352 NULL, 1353 0); 1354 SMC_RET1(handle, status); 1355 } 1356 1357 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1358 { 1359 uint64_t key_addr = x2; 1360 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1361 1362 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1363 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1364 status = INTEL_SIP_SMC_STATUS_REJECTED; 1365 SMC_RET1(handle, status); 1366 } 1367 1368 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1369 GET_JOB_ID(x1), 1370 MBOX_FCS_CREATE_CS_KEY, 1371 (uint32_t *)key_addr, 1372 key_len_words, 1373 MBOX_CMD_FLAG_CASUAL, 1374 sip_smc_cmd_cb_ret3, 1375 NULL, 1376 0); 1377 SMC_RET1(handle, status); 1378 } 1379 1380 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1381 { 1382 uint32_t session_id = (uint32_t)x2; 1383 uint32_t key_uid = (uint32_t)x3; 1384 uint64_t ret_key_addr = (uint64_t)x4; 1385 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1386 1387 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1388 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1389 status = INTEL_SIP_SMC_STATUS_REJECTED; 1390 SMC_RET1(handle, status); 1391 } 1392 1393 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1394 RESERVED_AS_ZERO, key_uid}; 1395 1396 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1397 GET_JOB_ID(x1), 1398 MBOX_FCS_EXPORT_CS_KEY, 1399 (uint32_t *)&payload, 1400 sizeof(payload) / MBOX_WORD_BYTE, 1401 MBOX_CMD_FLAG_CASUAL, 1402 sip_smc_ret_nbytes_cb, 1403 (uint32_t *)ret_key_addr, 1404 2); 1405 SMC_RET1(handle, status); 1406 } 1407 1408 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1409 { 1410 uint32_t session_id = (uint32_t)x2; 1411 uint32_t key_uid = (uint32_t)x3; 1412 1413 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1414 RESERVED_AS_ZERO, key_uid}; 1415 1416 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1417 GET_JOB_ID(x1), 1418 MBOX_FCS_REMOVE_CS_KEY, 1419 (uint32_t *)&payload, 1420 sizeof(payload) / MBOX_WORD_BYTE, 1421 MBOX_CMD_FLAG_CASUAL, 1422 sip_smc_cmd_cb_ret3, 1423 NULL, 1424 0); 1425 SMC_RET1(handle, status); 1426 } 1427 1428 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1429 { 1430 uint32_t session_id = (uint32_t)x2; 1431 uint32_t key_uid = (uint32_t)x3; 1432 uint64_t ret_key_addr = (uint64_t)x4; 1433 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1434 1435 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1436 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1437 status = INTEL_SIP_SMC_STATUS_REJECTED; 1438 SMC_RET1(handle, status); 1439 } 1440 1441 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1442 RESERVED_AS_ZERO, key_uid}; 1443 1444 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1445 GET_JOB_ID(x1), 1446 MBOX_FCS_GET_CS_KEY_INFO, 1447 (uint32_t *)&payload, 1448 sizeof(payload) / MBOX_WORD_BYTE, 1449 MBOX_CMD_FLAG_CASUAL, 1450 sip_smc_ret_nbytes_cb, 1451 (uint32_t *)ret_key_addr, 1452 2); 1453 SMC_RET1(handle, status); 1454 } 1455 1456 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1457 { 1458 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1459 x6, &mbox_error); 1460 SMC_RET1(handle, status); 1461 } 1462 1463 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1464 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1465 { 1466 uint32_t job_id = 0U; 1467 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1468 true : false; 1469 1470 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1471 x3, x4, x5, x6, x7, x8, is_final, 1472 &job_id, x9, x10); 1473 SMC_RET1(handle, status); 1474 } 1475 1476 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1477 { 1478 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1479 &mbox_error); 1480 SMC_RET1(handle, status); 1481 } 1482 1483 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1484 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1485 { 1486 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1487 true : false; 1488 1489 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1490 x3, x4, x5, x6, (uint32_t *) &x7, 1491 is_final, &mbox_error, x8); 1492 1493 SMC_RET1(handle, status); 1494 } 1495 1496 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1497 { 1498 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1499 &mbox_error); 1500 SMC_RET1(handle, status); 1501 } 1502 1503 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1504 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1505 { 1506 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1507 true : false; 1508 1509 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1510 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1511 is_final, &mbox_error, x9); 1512 SMC_RET1(handle, status); 1513 } 1514 1515 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1516 { 1517 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1518 &mbox_error); 1519 SMC_RET1(handle, status); 1520 } 1521 1522 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1523 { 1524 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1525 x4, x5, x6, (uint32_t *) &x7, 1526 &mbox_error); 1527 SMC_RET1(handle, status); 1528 } 1529 1530 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1531 { 1532 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1533 &mbox_error); 1534 SMC_RET1(handle, status); 1535 } 1536 1537 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1538 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1539 { 1540 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1541 ? true : false; 1542 1543 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1544 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1545 is_final, &mbox_error, x8); 1546 SMC_RET1(handle, status); 1547 } 1548 1549 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1550 { 1551 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1552 x6, &mbox_error); 1553 SMC_RET1(handle, status); 1554 } 1555 1556 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1557 { 1558 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1559 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1560 &mbox_error); 1561 SMC_RET1(handle, status); 1562 } 1563 1564 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1565 { 1566 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1567 x5, x6, &mbox_error); 1568 SMC_RET1(handle, status); 1569 } 1570 1571 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1572 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1573 { 1574 bool is_final = (smc_fid == 1575 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1576 true : false; 1577 1578 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1579 smc_fid, x1, x2, x3, x4, x5, x6, 1580 (uint32_t *) &x7, x8, is_final, 1581 &mbox_error, x9); 1582 SMC_RET1(handle, status); 1583 } 1584 1585 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1586 { 1587 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1588 &mbox_error); 1589 SMC_RET1(handle, status); 1590 } 1591 1592 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1593 { 1594 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1595 x4, (uint32_t *) &x5, &mbox_error); 1596 SMC_RET1(handle, status); 1597 } 1598 1599 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1600 { 1601 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1602 &mbox_error); 1603 SMC_RET1(handle, status); 1604 } 1605 1606 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1607 { 1608 uint32_t dest_size = (uint32_t)x7; 1609 1610 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1611 __func__, __LINE__, (uint32_t)x7, dest_size); 1612 1613 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1614 x4, x5, x6, (uint32_t *) &dest_size, 1615 &mbox_error); 1616 SMC_RET1(handle, status); 1617 } 1618 1619 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1620 { 1621 uint32_t *src_addr = (uint32_t *)x2; 1622 uint32_t src_size = (uint32_t)x3; 1623 uint32_t *dst_addr = (uint32_t *)x4; 1624 1625 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1626 GET_JOB_ID(x1), 1627 MBOX_CMD_MCTP_MSG, 1628 src_addr, 1629 src_size / MBOX_WORD_BYTE, 1630 MBOX_CMD_FLAG_CASUAL, 1631 sip_smc_ret_nbytes_cb, 1632 dst_addr, 1633 2); 1634 1635 SMC_RET1(handle, status); 1636 } 1637 1638 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1639 { 1640 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1641 x7); 1642 SMC_RET1(handle, status); 1643 } 1644 1645 default: 1646 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1647 cookie, handle, flags); 1648 } /* switch (smc_fid) */ 1649 } 1650 #endif 1651 1652 /* 1653 * This function is responsible for handling all SiP calls from the NS world 1654 */ 1655 1656 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1657 u_register_t x1, 1658 u_register_t x2, 1659 u_register_t x3, 1660 u_register_t x4, 1661 void *cookie, 1662 void *handle, 1663 u_register_t flags) 1664 { 1665 uint32_t retval = 0, completed_addr[3]; 1666 uint32_t retval2 = 0; 1667 uint32_t mbox_error = 0; 1668 uint32_t err_states = 0; 1669 uint64_t retval64, rsu_respbuf[9]; 1670 uint32_t seu_respbuf[3]; 1671 int status = INTEL_SIP_SMC_STATUS_OK; 1672 int mbox_status; 1673 unsigned int len_in_resp; 1674 u_register_t x5, x6, x7; 1675 1676 switch (smc_fid) { 1677 case SIP_SVC_UID: 1678 /* Return UID to the caller */ 1679 SMC_UUID_RET(handle, intl_svc_uid); 1680 1681 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1682 status = intel_mailbox_fpga_config_isdone(&err_states); 1683 SMC_RET4(handle, status, err_states, 0, 0); 1684 1685 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1686 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1687 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1688 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1689 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1690 1691 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1692 status = intel_fpga_config_start(x1); 1693 SMC_RET4(handle, status, 0, 0, 0); 1694 1695 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1696 status = intel_fpga_config_write(x1, x2); 1697 SMC_RET4(handle, status, 0, 0, 0); 1698 1699 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1700 status = intel_fpga_config_completed_write(completed_addr, 1701 &retval, &rcv_id); 1702 switch (retval) { 1703 case 1: 1704 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1705 completed_addr[0], 0, 0); 1706 1707 case 2: 1708 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1709 completed_addr[0], 1710 completed_addr[1], 0); 1711 1712 case 3: 1713 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1714 completed_addr[0], 1715 completed_addr[1], 1716 completed_addr[2]); 1717 1718 case 0: 1719 SMC_RET4(handle, status, 0, 0, 0); 1720 1721 default: 1722 mailbox_clear_response(); 1723 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1724 } 1725 1726 case INTEL_SIP_SMC_REG_READ: 1727 status = intel_secure_reg_read(x1, &retval); 1728 SMC_RET3(handle, status, retval, x1); 1729 1730 case INTEL_SIP_SMC_REG_WRITE: 1731 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 1732 SMC_RET3(handle, status, retval, x1); 1733 1734 case INTEL_SIP_SMC_REG_UPDATE: 1735 status = intel_secure_reg_update(x1, (uint32_t)x2, 1736 (uint32_t)x3, &retval); 1737 SMC_RET3(handle, status, retval, x1); 1738 1739 case INTEL_SIP_SMC_RSU_STATUS: 1740 status = intel_rsu_status(rsu_respbuf, 1741 ARRAY_SIZE(rsu_respbuf)); 1742 if (status) { 1743 SMC_RET1(handle, status); 1744 } else { 1745 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 1746 rsu_respbuf[2], rsu_respbuf[3]); 1747 } 1748 1749 case INTEL_SIP_SMC_RSU_UPDATE: 1750 status = intel_rsu_update(x1); 1751 SMC_RET1(handle, status); 1752 1753 case INTEL_SIP_SMC_RSU_NOTIFY: 1754 status = intel_rsu_notify(x1); 1755 SMC_RET1(handle, status); 1756 1757 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 1758 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 1759 ARRAY_SIZE(rsu_respbuf), &retval); 1760 if (status) { 1761 SMC_RET1(handle, status); 1762 } else { 1763 SMC_RET2(handle, status, retval); 1764 } 1765 1766 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 1767 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1768 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 1769 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 1770 1771 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 1772 status = intel_rsu_copy_dcmf_version(x1, x2); 1773 SMC_RET1(handle, status); 1774 1775 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 1776 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 1777 ARRAY_SIZE(rsu_respbuf)); 1778 if (status) { 1779 SMC_RET1(handle, status); 1780 } else { 1781 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 1782 rsu_respbuf[2], rsu_respbuf[3]); 1783 } 1784 1785 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 1786 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 1787 ((uint64_t)rsu_dcmf_stat[3] << 48) | 1788 ((uint64_t)rsu_dcmf_stat[2] << 32) | 1789 ((uint64_t)rsu_dcmf_stat[1] << 16) | 1790 rsu_dcmf_stat[0]); 1791 1792 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 1793 status = intel_rsu_copy_dcmf_status(x1); 1794 SMC_RET1(handle, status); 1795 1796 case INTEL_SIP_SMC_RSU_MAX_RETRY: 1797 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 1798 1799 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 1800 rsu_max_retry = x1; 1801 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 1802 1803 case INTEL_SIP_SMC_ECC_DBE: 1804 status = intel_ecc_dbe_notification(x1); 1805 SMC_RET1(handle, status); 1806 1807 case INTEL_SIP_SMC_SERVICE_COMPLETED: 1808 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 1809 &len_in_resp, &mbox_error); 1810 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 1811 1812 case INTEL_SIP_SMC_FIRMWARE_VERSION: 1813 status = intel_smc_fw_version(&retval); 1814 SMC_RET2(handle, status, retval); 1815 1816 case INTEL_SIP_SMC_MBOX_SEND_CMD: 1817 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1818 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1819 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 1820 &mbox_status, &len_in_resp); 1821 SMC_RET3(handle, status, mbox_status, len_in_resp); 1822 1823 case INTEL_SIP_SMC_GET_USERCODE: 1824 status = intel_smc_get_usercode(&retval); 1825 SMC_RET2(handle, status, retval); 1826 1827 case INTEL_SIP_SMC_FCS_CRYPTION: 1828 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1829 1830 if (x1 == FCS_MODE_DECRYPT) { 1831 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 1832 } else if (x1 == FCS_MODE_ENCRYPT) { 1833 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 1834 } else { 1835 status = INTEL_SIP_SMC_STATUS_REJECTED; 1836 } 1837 1838 SMC_RET3(handle, status, x4, x5); 1839 1840 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 1841 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1842 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1843 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1844 1845 if (x3 == FCS_MODE_DECRYPT) { 1846 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 1847 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 1848 } else if (x3 == FCS_MODE_ENCRYPT) { 1849 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 1850 (uint32_t *) &x7, &mbox_error, 0, 0); 1851 } else { 1852 status = INTEL_SIP_SMC_STATUS_REJECTED; 1853 } 1854 1855 SMC_RET4(handle, status, mbox_error, x6, x7); 1856 1857 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 1858 status = intel_fcs_random_number_gen(x1, &retval64, 1859 &mbox_error); 1860 SMC_RET4(handle, status, mbox_error, x1, retval64); 1861 1862 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 1863 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 1864 &send_id); 1865 SMC_RET1(handle, status); 1866 1867 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 1868 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 1869 SMC_RET1(handle, status); 1870 1871 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 1872 status = intel_fcs_get_provision_data(&send_id); 1873 SMC_RET1(handle, status); 1874 1875 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 1876 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 1877 &mbox_error); 1878 SMC_RET2(handle, status, mbox_error); 1879 1880 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 1881 status = intel_hps_set_bridges(x1, x2); 1882 SMC_RET1(handle, status); 1883 1884 case INTEL_SIP_SMC_HWMON_READTEMP: 1885 status = intel_hwmon_readtemp(x1, &retval); 1886 SMC_RET2(handle, status, retval); 1887 1888 case INTEL_SIP_SMC_HWMON_READVOLT: 1889 status = intel_hwmon_readvolt(x1, &retval); 1890 SMC_RET2(handle, status, retval); 1891 1892 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 1893 status = intel_fcs_sigma_teardown(x1, &mbox_error); 1894 SMC_RET2(handle, status, mbox_error); 1895 1896 case INTEL_SIP_SMC_FCS_CHIP_ID: 1897 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 1898 SMC_RET4(handle, status, mbox_error, retval, retval2); 1899 1900 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 1901 status = intel_fcs_attestation_subkey(x1, x2, x3, 1902 (uint32_t *) &x4, &mbox_error); 1903 SMC_RET4(handle, status, mbox_error, x3, x4); 1904 1905 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 1906 status = intel_fcs_get_measurement(x1, x2, x3, 1907 (uint32_t *) &x4, &mbox_error); 1908 SMC_RET4(handle, status, mbox_error, x3, x4); 1909 1910 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 1911 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 1912 (uint32_t *) &x3, &mbox_error); 1913 SMC_RET4(handle, status, mbox_error, x2, x3); 1914 1915 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 1916 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 1917 SMC_RET2(handle, status, mbox_error); 1918 1919 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 1920 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 1921 SMC_RET3(handle, status, mbox_error, retval); 1922 1923 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1924 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1925 SMC_RET2(handle, status, mbox_error); 1926 1927 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1928 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1929 SMC_RET1(handle, status); 1930 1931 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1932 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1933 (uint32_t *) &x4, &mbox_error); 1934 SMC_RET4(handle, status, mbox_error, x3, x4); 1935 1936 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1937 status = intel_fcs_remove_crypto_service_key(x1, x2, 1938 &mbox_error); 1939 SMC_RET2(handle, status, mbox_error); 1940 1941 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1942 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1943 (uint32_t *) &x4, &mbox_error); 1944 SMC_RET4(handle, status, mbox_error, x3, x4); 1945 1946 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1947 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1948 status = intel_fcs_get_digest_init(x1, x2, x3, 1949 x4, x5, &mbox_error); 1950 SMC_RET2(handle, status, mbox_error); 1951 1952 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1953 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1954 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1955 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 1956 x3, x4, x5, (uint32_t *) &x6, false, 1957 &mbox_error, 0); 1958 SMC_RET4(handle, status, mbox_error, x5, x6); 1959 1960 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1961 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1962 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1963 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 1964 x3, x4, x5, (uint32_t *) &x6, true, 1965 &mbox_error, 0); 1966 SMC_RET4(handle, status, mbox_error, x5, x6); 1967 1968 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1969 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1970 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1971 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1972 x4, x5, (uint32_t *) &x6, false, 1973 &mbox_error, &send_id); 1974 SMC_RET4(handle, status, mbox_error, x5, x6); 1975 1976 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1977 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1978 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1979 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1980 x4, x5, (uint32_t *) &x6, true, 1981 &mbox_error, &send_id); 1982 SMC_RET4(handle, status, mbox_error, x5, x6); 1983 1984 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1985 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1986 status = intel_fcs_mac_verify_init(x1, x2, x3, 1987 x4, x5, &mbox_error); 1988 SMC_RET2(handle, status, mbox_error); 1989 1990 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1991 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1992 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1993 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1994 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 1995 x3, x4, x5, (uint32_t *) &x6, x7, false, 1996 &mbox_error, 0); 1997 SMC_RET4(handle, status, mbox_error, x5, x6); 1998 1999 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2000 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2001 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2002 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2003 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2004 x3, x4, x5, (uint32_t *) &x6, x7, true, 2005 &mbox_error, 0); 2006 SMC_RET4(handle, status, mbox_error, x5, x6); 2007 2008 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2009 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2010 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2011 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2012 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2013 x4, x5, (uint32_t *) &x6, x7, 2014 false, &mbox_error, &send_id); 2015 SMC_RET4(handle, status, mbox_error, x5, x6); 2016 2017 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2018 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2019 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2020 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2021 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2022 x4, x5, (uint32_t *) &x6, x7, 2023 true, &mbox_error, &send_id); 2024 SMC_RET4(handle, status, mbox_error, x5, x6); 2025 2026 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2027 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2028 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2029 x4, x5, &mbox_error); 2030 SMC_RET2(handle, status, mbox_error); 2031 2032 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2033 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2034 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2035 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2036 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2037 false, &mbox_error, 0); 2038 SMC_RET4(handle, status, mbox_error, x5, x6); 2039 2040 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2041 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2042 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2043 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2044 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2045 true, &mbox_error, 0); 2046 SMC_RET4(handle, status, mbox_error, x5, x6); 2047 2048 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2049 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2050 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2051 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2052 x2, x3, x4, x5, (uint32_t *) &x6, false, 2053 &mbox_error, &send_id); 2054 SMC_RET4(handle, status, mbox_error, x5, x6); 2055 2056 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2057 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2058 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2059 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2060 x2, x3, x4, x5, (uint32_t *) &x6, true, 2061 &mbox_error, &send_id); 2062 SMC_RET4(handle, status, mbox_error, x5, x6); 2063 2064 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2065 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2066 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2067 x4, x5, &mbox_error); 2068 SMC_RET2(handle, status, mbox_error); 2069 2070 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2071 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2072 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2073 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2074 x3, x4, x5, (uint32_t *) &x6, 2075 &mbox_error); 2076 SMC_RET4(handle, status, mbox_error, x5, x6); 2077 2078 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2079 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2080 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2081 x4, x5, &mbox_error); 2082 SMC_RET2(handle, status, mbox_error); 2083 2084 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2085 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2086 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2087 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2088 x2, x3, x4, x5, (uint32_t *) &x6, 2089 &mbox_error); 2090 SMC_RET4(handle, status, mbox_error, x5, x6); 2091 2092 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2093 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2094 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2095 x4, x5, &mbox_error); 2096 SMC_RET2(handle, status, mbox_error); 2097 2098 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2099 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2100 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2101 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2102 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2103 smc_fid, 0, x1, x2, x3, x4, x5, 2104 (uint32_t *) &x6, x7, false, 2105 &mbox_error, 0); 2106 SMC_RET4(handle, status, mbox_error, x5, x6); 2107 2108 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2109 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2110 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2111 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2112 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2113 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2114 x7, false, &mbox_error, &send_id); 2115 SMC_RET4(handle, status, mbox_error, x5, x6); 2116 2117 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2118 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2119 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2120 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2121 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2122 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2123 x7, true, &mbox_error, &send_id); 2124 SMC_RET4(handle, status, mbox_error, x5, x6); 2125 2126 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2127 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2128 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2129 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2130 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2131 smc_fid, 0, x1, x2, x3, x4, x5, 2132 (uint32_t *) &x6, x7, true, 2133 &mbox_error, 0); 2134 SMC_RET4(handle, status, mbox_error, x5, x6); 2135 2136 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2137 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2138 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2139 x4, x5, &mbox_error); 2140 SMC_RET2(handle, status, mbox_error); 2141 2142 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2143 status = intel_fcs_ecdsa_get_pubkey_finalize( 2144 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2145 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2146 SMC_RET4(handle, status, mbox_error, x3, x4); 2147 2148 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2149 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2150 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2151 x4, x5, &mbox_error); 2152 SMC_RET2(handle, status, mbox_error); 2153 2154 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2155 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2156 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2157 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2158 x4, x5, (uint32_t *) &x6, &mbox_error); 2159 SMC_RET4(handle, status, mbox_error, x5, x6); 2160 2161 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2162 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2163 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2164 &mbox_error); 2165 SMC_RET2(handle, status, mbox_error); 2166 2167 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2168 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2169 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2170 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2171 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2172 SMC_RET1(handle, status); 2173 2174 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2175 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2176 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2177 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2178 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2179 SMC_RET1(handle, status); 2180 2181 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2182 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2183 status = intel_smmu_hps_remapper_config(x1); 2184 SMC_RET1(handle, status); 2185 #endif 2186 2187 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2188 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2189 &mbox_error); 2190 SMC_RET4(handle, status, mbox_error, x1, retval64); 2191 2192 case INTEL_SIP_SMC_SVC_VERSION: 2193 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2194 SIP_SVC_VERSION_MAJOR, 2195 SIP_SVC_VERSION_MINOR); 2196 2197 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2198 status = intel_sdm_seu_err_read(seu_respbuf, 2199 ARRAY_SIZE(seu_respbuf)); 2200 if (status) { 2201 SMC_RET1(handle, status); 2202 } else { 2203 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2204 } 2205 2206 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2207 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2208 SMC_RET1(handle, status); 2209 2210 case INTEL_SIP_SMC_ATF_BUILD_VER: 2211 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2212 VERSION_MINOR, VERSION_PATCH); 2213 2214 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2215 case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR: 2216 intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2); 2217 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2218 #endif 2219 2220 default: 2221 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2222 cookie, handle, flags); 2223 } 2224 } 2225 2226 uintptr_t sip_smc_handler(uint32_t smc_fid, 2227 u_register_t x1, 2228 u_register_t x2, 2229 u_register_t x3, 2230 u_register_t x4, 2231 void *cookie, 2232 void *handle, 2233 u_register_t flags) 2234 { 2235 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2236 2237 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2238 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2239 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2240 cookie, handle, flags); 2241 } 2242 #if SIP_SVC_V3 2243 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2244 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2245 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2246 cookie, handle, flags); 2247 return ret; 2248 } 2249 #endif 2250 else { 2251 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2252 cookie, handle, flags); 2253 } 2254 } 2255 2256 DECLARE_RT_SVC( 2257 socfpga_sip_svc, 2258 OEN_SIP_START, 2259 OEN_SIP_END, 2260 SMC_TYPE_FAST, 2261 NULL, 2262 sip_smc_handler 2263 ); 2264 2265 DECLARE_RT_SVC( 2266 socfpga_sip_svc_std, 2267 OEN_SIP_START, 2268 OEN_SIP_END, 2269 SMC_TYPE_YIELD, 2270 NULL, 2271 sip_smc_handler 2272 ); 2273