| b726c169 | 11-May-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
plat/arm: Introduce ARM_LINUX_KERNEL_AS_BL33 build option
Normally, BL33 needs to contain a boot loader like U-Boot or UEFI that
eventually gives control to the OS. However, in some cases, this boot
plat/arm: Introduce ARM_LINUX_KERNEL_AS_BL33 build option
Normally, BL33 needs to contain a boot loader like U-Boot or UEFI that
eventually gives control to the OS. However, in some cases, this boot
sequence may be too slow. For example, when doing tests in a
cycle-accurate emulator, the user may only be interested in the
interaction between the Trusted Firmware and the OS, not in the boot
process itself.
The new option ARM_LINUX_KERNEL_AS_BL33 allows BL33 to contain the Linux
kernel image by changing the value of registers x0-x3 to the values
expected by the kernel. This option requires the device tree blob (DTB)
to be present in memory. Its address must be specified in the newly
introduced ARM_PRELOADED_DTB_BASE build option. For now, it only supports
AArch64 kernels.
This option is only available when RESET_TO_BL31=1. For this reason
the BL33 binary must be preloaded in memory and PRELOADED_BL33_BASE must
be used.
For example, if the kernel is loaded at 0x80080000 and the DTB is loaded
at address 0x82000000, the firmware could be built like this:
CROSS_COMPILE=aarch64-linux-gnu- \
make PLAT=fvp DEBUG=1 \
RESET_TO_BL31=1 \
ARM_LINUX_KERNEL_AS_BL33=1 \
PRELOADED_BL33_BASE=0x80080000 \
ARM_PRELOADED_DTB_BASE=0x82000000 \
all fip
Change-Id: If9dc847c65ae2d0c27b51f0fd44fc06b28497db9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 2f18aa1f | 04-May-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
plat/arm: Migrate AArch64 port to the multi console driver
The old API is deprecated and will eventually be removed.
Arm platforms now use the multi console driver for boot and runtime
consoles. Ho
plat/arm: Migrate AArch64 port to the multi console driver
The old API is deprecated and will eventually be removed.
Arm platforms now use the multi console driver for boot and runtime
consoles. However, the crash console uses the direct console API because
it doesn't need any memory access to work. This makes it more robust
during crashes.
The AArch32 port of the Trusted Firmware doesn't support this new API
yet, so it is only enabled in AArch64 builds. Because of this, the
common code must maintain compatibility with both systems. SP_MIN
doesn't have to be updated because it's only used in AArch32 builds.
The TSP is only used in AArch64, so it only needs to support the new
API without keeping support for the old one.
Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this
causes the UARTs to reset (except for the one used by the TSP). This
means that they must be unregistered when suspending and re-registered
when resuming. This wasn't a problem with the old driver because it just
restarted the UART, and there were no problems associated with
registering and unregistering consoles.
The size of BL31 has been increased in builds with SPM.
Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 0b9ce906 | 06-Feb-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM Platforms: Support RAS
- Assign 0x10 for RAS exceptions on ARM platforms, and install
EHF priority descriptor.
- Call the common RAS initialisation from ARM BL31 setup.
- Add empty d
ARM Platforms: Support RAS
- Assign 0x10 for RAS exceptions on ARM platforms, and install
EHF priority descriptor.
- Call the common RAS initialisation from ARM BL31 setup.
- Add empty definitions for platform error records and RAS interrupts.
Change-Id: I0675f299b7840be4c83a9c7a81073a95c605dc90
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
show more ...
|
| 638b034c | 05-Jan-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
ARM platforms: Demonstrate mem_protect from el3_runtime
Previously mem_protect used to be only supported from BL2. This is not
helpful in the case when ARM TF-A BL2 is not used. This patch demonstra
ARM platforms: Demonstrate mem_protect from el3_runtime
Previously mem_protect used to be only supported from BL2. This is not
helpful in the case when ARM TF-A BL2 is not used. This patch demonstrates
mem_protect from el3_runtime firmware on ARM Platforms specifically
when RESET_TO_BL31 or RESET_TO_SP_MIN flag is set as BL2 may be absent
in these cases. The Non secure DRAM is dynamically mapped into EL3 mmap
tables temporarily and then the protected regions are then cleared. This
avoids the need to map the non secure DRAM permanently to BL31/sp_min.
The stack size is also increased, because DYNAMIC_XLAT_TABLES require
a bigger stack.
Change-Id: Ia44c594192ed5c5adc596c0cff2c7cc18c001fde
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
show more ...
|
| bb3a6f8c | 16-Apr-2018 |
Sudipto Paul <sudipto.paul@arm.com> |
css/sgi575: enable ARM_PLAT_MT flag
SGI-575 platform is based on Cortex-A75 processor which has its MT bit
in the MPIDR register set to '1'. So the Arm platform layer code has
to be made aware of th
css/sgi575: enable ARM_PLAT_MT flag
SGI-575 platform is based on Cortex-A75 processor which has its MT bit
in the MPIDR register set to '1'. So the Arm platform layer code has
to be made aware of this.
Signed-off-by: Sudipto Paul <sudipto.paul@arm.com>
show more ...
|
| 4af16543 | 16-Apr-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1346 from samarthp/sp/support-multiple-mhu-gen
plat/arm: Add MHUv2 support to SCMI driver |
| a427785c | 23-Nov-2017 |
Samarth Parikh <samarth.parikh@arm.com> |
plat/arm: Add MHUv2 support to SCMI driver
Currently the SCMI driver supports MHUv1, but Arm platforms may have
varied versions of MHU driver, with MHUv2 controllers being in the
latest Arm platform
plat/arm: Add MHUv2 support to SCMI driver
Currently the SCMI driver supports MHUv1, but Arm platforms may have
varied versions of MHU driver, with MHUv2 controllers being in the
latest Arm platforms.
This patch updates the SCMI driver to support MHUv2, specifically that
the sender must send the wake-up to the receiver before initiating any
data transfer.
Also, the existing mhu driver files, css_mhu.c and css_mhu.h, have been
moved from the scpi directory to a new directory, css/drivers/mhu.
Change-Id: I9b46b492a3e1d9e26db12d83a9773958a8c8402f
Signed-off-by: Samarth Parikh <samarth.parikh@arm.com>
show more ...
|
| 8b371200 | 16-Apr-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1356 from robertovargas-arm/misra-changes
Misra changes |
| 3b94189a | 12-Feb-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Fix MISRA rule 8.4 Part 4
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined
Fixed for:
make DEBUG=1 PLAT=fvp SPD=tspd TRUSTE
Fix MISRA rule 8.4 Part 4
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined
Fixed for:
make DEBUG=1 PLAT=fvp SPD=tspd TRUSTED_BOARD_BOOT=1 \
GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \
ROT_KEY=arm_rotprivk_rsa.pem MBEDTLS_DIR=mbedtls all
Change-Id: Ie4cd6011b3e4fdcdd94ccb97a7e941f3b5b7aeb8
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
show more ...
|
| 1a29f938 | 12-Feb-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Fix MISRA rule 8.4 Part 3
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined
Fixed for:
make DEBUG=1 PLAT=fvp SPD=tspd all
C
Fix MISRA rule 8.4 Part 3
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined
Fixed for:
make DEBUG=1 PLAT=fvp SPD=tspd all
Change-Id: I0a16cf68fef29cf00ec0a52e47786f61d02ca4ae
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
show more ...
|
| f37704bc | 12-Feb-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Fix MISRA rule 8.3 Part 2
Rule 8.3: All declarations of an object or function shall
use the same names and type qualifiers.
Fixed for:
make DEBUG=1 PLAT=juno LOG_LEVEL=50 all
Change-Id:
Fix MISRA rule 8.3 Part 2
Rule 8.3: All declarations of an object or function shall
use the same names and type qualifiers.
Fixed for:
make DEBUG=1 PLAT=juno LOG_LEVEL=50 all
Change-Id: I0e4a03a0d2170cb1c632e079112a972091994a39
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
show more ...
|
| 35a3eeb6 | 12-Feb-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Fix MISRA rule 8.4 Part 1
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined
Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 al
Fix MISRA rule 8.4 Part 1
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined
Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all
Change-Id: I32b223251b8bf5924149d89431a65d3405a73d3e
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
show more ...
|
| 0f17a683 | 12-Apr-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1347 from davidcunado-arm/dc/affinities
FVP: Fix function for translating MPIDR to linear index |
| b47f941d | 11-Apr-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1342 from Summer-ARM/sq/support-tzmp1
support tzmp1 |
| 60a23fd8 | 02-Mar-2018 |
Summer Qin <summer.qin@arm.com> |
Juno: Add support for TrustZone Media Protection 1 (TZMP1)
Add TZMP1 support on Juno and increase the BL2 size accordingly due to the
extra data structures to describe the TZC regions and the additi
Juno: Add support for TrustZone Media Protection 1 (TZMP1)
Add TZMP1 support on Juno and increase the BL2 size accordingly due to the
extra data structures to describe the TZC regions and the additional code.
Signed-off-by: Summer Qin <summer.qin@arm.com>
show more ...
|
| 23411d2c | 12-Mar-2018 |
Summer Qin <summer.qin@arm.com> |
plat/arm: Allow override of default TZC regions
This patch allows the ARM Platforms to specify the TZC regions to be
specified to the ARM TZC helpers in arm_tzc400.c and arm_tzc_dmc500.c.
If the reg
plat/arm: Allow override of default TZC regions
This patch allows the ARM Platforms to specify the TZC regions to be
specified to the ARM TZC helpers in arm_tzc400.c and arm_tzc_dmc500.c.
If the regions are not specified then the default TZC region will be
configured by these helpers.
This override mechanism allows specifying special regions for TZMP1
usecase.
Signed-off-by: Summer Qin <summer.qin@arm.com>
show more ...
|
| 83a2376e | 23-Mar-2018 |
Amit Daniel Kachhap <amit.kachhap@arm.com> |
Juno: Increase bl2 max size to fix build when SPD=opteed
Building TBBR(SPD=opteed) and non-TBBR TF-A images is breaking for
Juno for different configurations listed below:
* Overflow error of 4096
Juno: Increase bl2 max size to fix build when SPD=opteed
Building TBBR(SPD=opteed) and non-TBBR TF-A images is breaking for
Juno for different configurations listed below:
* Overflow error of 4096 bytes for rsa algorithm.
* Overflow error of 8192 bytes for ecdsa algorithm.
* Overflow error of 4096 bytes for rsa+ecdsa algorithm.
* Overflow error of 4096 bytes for non-TBBR case.
So this patch increments macro PLAT_ARM_MAX_BL2_SIZE for all the above
cases accordingly.
Change-Id: I75ec6c0a718181d34553fe55437f0496f467683f
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
show more ...
|
| 468bea41 | 05-Apr-2018 |
David Cunado <david.cunado@arm.com> |
FVP: Fix function for translating MPIDR to linear index
The current AArch32 version of plat_arm_calc_core_pos uses an incorrect
algorithm to calculate the linear position of a core / PE from its
MPI
FVP: Fix function for translating MPIDR to linear index
The current AArch32 version of plat_arm_calc_core_pos uses an incorrect
algorithm to calculate the linear position of a core / PE from its
MPIDR.
This patch corrects the algorithm to:
(ClusterId * FVP_MAX_CPUS_PER_CLUSTER) * FVP_MAX_PE_PER_CPU
+ (CPUId * FVP_MAX_PE_PER_CPU)
+ ThreadId
which supports cores where there are more than 1 PE per CPU.
NOTE: the AArch64 version was fixed in 39b21d1
Change-Id: I72aea89d8f72f8b1fef54e2177a0fa6fef0f5513
Signed-off-by: David Cunado <david.cunado@arm.com>
show more ...
|
| 02f8c038 | 29-Mar-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1327 from npoushin/npoushin/sgi575
ARM platforms: Add support for SGI575 |
| b44cfc6d | 26-Feb-2018 |
Nariman Poushin <nariman.poushin@linaro.org> |
ARM platforms: Add support for SGI575
Add support for System Guidance for Infrastructure platform SGI575.
Change-Id: I0125c2ed4469fbc8367dafcc8adce770b6b3147d
Signed-off-by: Nariman Poushin <narima
ARM platforms: Add support for SGI575
Add support for System Guidance for Infrastructure platform SGI575.
Change-Id: I0125c2ed4469fbc8367dafcc8adce770b6b3147d
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
show more ...
|
| 649c48f5 | 14-Mar-2018 |
Jonathan Wright <jonathan.wright@arm.com> |
plat: fix switch statements to comply with MISRA rules
Ensure (where possible) that switch statements in plat comply with MISRA
rules 16.1 - 16.7.
Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a75539162
plat: fix switch statements to comply with MISRA rules
Ensure (where possible) that switch statements in plat comply with MISRA
rules 16.1 - 16.7.
Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
show more ...
|
| 0f66bbf2 | 22-Mar-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1307 from wangfeng-64/master
FVP: change the method for translating MPIDR values to a linear indices |
| 085e80ec | 21-Mar-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Rename 'smcc' to 'smccc'
When the source code says 'SMCC' it is talking about the SMC Calling
Convention. The correct acronym is SMCCC. This affects a few definitions
and file names.
Some files hav
Rename 'smcc' to 'smccc'
When the source code says 'SMCC' it is talking about the SMC Calling
Convention. The correct acronym is SMCCC. This affects a few definitions
and file names.
Some files have been renamed (smcc.h, smcc_helpers.h and smcc_macros.S)
but the old files have been kept for compatibility, they include the
new ones with an ERROR_DEPRECATED guard.
Change-Id: I78f94052a502436fdd97ca32c0fe86bd58173f2f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
show more ...
|
| 39b21d19 | 15-Mar-2018 |
Wang Feng <feng_feng.wang@spreadtrum.com> |
FVP: change the method for translating MPIDR values to a linear indices
x3 will be assigned by the folloing instructions.
So the first instruction is not needed any more.
old method:
(ClusterId *
FVP: change the method for translating MPIDR values to a linear indices
x3 will be assigned by the folloing instructions.
So the first instruction is not needed any more.
old method:
(ClusterId * FVP_MAX_CPUS_PER_CLUSTER)
+ (CPUId * FVP_MAX_PE_PER_CPU)
+ ThreadId
it should be
(ClusterId * FVP_MAX_CPUS_PER_CLUSTER) * FVP_MAX_PE_PER_CPU
+ (CPUId * FVP_MAX_PE_PER_CPU)
+ ThreadId
which can be simplified as:
(ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU + ThreadId
Signed-off-by: Wang Feng <feng_feng.wang@spreadtrum.com>
show more ...
|
| 950c6956 | 15-Mar-2018 |
Joel Hutton <Joel.Hutton@Arm.com> |
FVP AArch32: Fix flash access in BL32 for mem_protect
The FVP platform port for SP_MIN (BL32) didn't map the flash memory
in BL32 for stroring the mem_protect enable state information leading
to syn
FVP AArch32: Fix flash access in BL32 for mem_protect
The FVP platform port for SP_MIN (BL32) didn't map the flash memory
in BL32 for stroring the mem_protect enable state information leading
to synchronous exception. The patch fixes it by adding the region to
the BL32 mmap tables.
Change-Id: I37eec83c3e1ea43d1b5504d3683eebc32a57eadf
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
show more ...
|