fix(fvp): adjust BL2 maximum size as per total SRAM size

Adjusted BL2 maximum size as per total SRAM size.

Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Man

fix(fvp): adjust BL2 maximum size as per total SRAM size

Adjusted BL2 maximum size as per total SRAM size.

Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(mte): adds feature detection for MTE_PERM

Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.

Change-Id: If24b42

feat(mte): adds feature detection for MTE_PERM

Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.

Change-Id: If24b42f1207154e639016b0b840b2d91c6ee13d4
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(fvp): update system suspend in OS-initiated mode

This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR

fix(fvp): update system suspend in OS-initiated mode

This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.

This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.

Change-Id: Ia0fb1e68af9320370325642b17c4569e9580aa3a
Signed-off-by: Wing Li <wingers@google.com>

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refactor(fvp): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signe

refactor(fvp): update RSS driver inteface calls

In order to comply with the previous RSS driver change,
interface calls have been updated.

Change-Id: I0a1f3c6a6f8017468d86903cc0158805c6461c28
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <M

fix(fvp): adjust BL31 maximum size as per total SRAM size

Adjusted BL31 maximum size as per total SRAM size.

Change-Id: Ifdfdedb8af3e001cebba8e60c973f3c72be11652
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(fvp): allow configurable FVP Trusted SRAM size" into integration

Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve dir

Merge changes from topic "ffa_el3_spmc_fixes" into integration

* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve direct messaging validation

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fix(el3-spm): fix LSP direct message response

Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id

fix(el3-spm): fix LSP direct message response

Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I482c08d4657617adb00b0f3cf3c8ddc84f1bf7c8

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feat(fvp): allow configurable FVP Trusted SRAM size

In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you t

feat(fvp): allow configurable FVP Trusted SRAM size

In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you to configure a larger Trusted SRAM of 512KB.

This change introduces the `FVP_TRUSTED_SRAM_SIZE` build option, which
allows you to explicitly specify how much of the Trusted SRAM to
utilise, e.g.:

FVP_TRUSTED_SRAM_SIZE=384

This allows previously-failing configurations to build successfully by
utilising more than the originally-allocated 256KB of the Trusted SRAM
while maintaining compatibility with older configurations/models that
only require/have 256KB.

Change-Id: I8344d3718564cd2bd53f1e6860e2fe341ae240b0
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(build): include Cortex-A78AE cpu file for FVP" into integration

feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Cha

feat(fvp): add mbedtls_asn1_get_len symbol in ROMlib

mbedtls_asn1_get_len() will be needed by the X.509 parser in an
upcoming patch.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I14310c80033a1142a94c0c4b54d63331479b643d

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Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update p

Merge changes from topic "psci-osi" into integration

* changes:
fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
fix(sc7280): update pwr_domain_suspend
fix(fvp): update pwr_domain_suspend

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refactor(fvp): nv ctr addr static helper function

Adding a static helper function plat_get_nv_ctr_addr() to be used by
both plat_set_nv_ctr() and plat_get_nv_ctr() to return the
non-volatile counter

refactor(fvp): nv ctr addr static helper function

Adding a static helper function plat_get_nv_ctr_addr() to be used by
both plat_set_nv_ctr() and plat_get_nv_ctr() to return the
non-volatile counter address stored in the platform.

Change-Id: I5124c19e4537bb369724aa0160cc55a3cb1ab7eb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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fix(fvp): update pwr_domain_suspend

Change-Id: Ied4063ac6e685368818b2296c2d1800f4b272b86
Signed-off-by: Wing Li <wingers@google.com>

feat(fvp): mock support for CCA NV ctr

AEM FVP does not have a third CCA NV counter so the
implementation will fake it by returning the Trusted
NV counter value when the caller requests the CCA NV
c

feat(fvp): mock support for CCA NV ctr

AEM FVP does not have a third CCA NV counter so the
implementation will fake it by returning the Trusted
NV counter value when the caller requests the CCA NV
counter. This allows us to use the CCA CoT on AEM FVP
nonetheless.

The FVP platform port now gets its own version of
plat_get_nv_ctr() as it now need to diverge from the
common implementation provided at the Arm development
platforms level.

Change-Id: I3258f837249a539d943d6d783406ba222bd4554e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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fix(build): include Cortex-A78AE cpu file for FVP

So far, the FVP platform.mk file did not include the corresponding file
for Cortex-A78AE, causing the FVP to hang when executing the
plat_reset_hand

fix(build): include Cortex-A78AE cpu file for FVP

So far, the FVP platform.mk file did not include the corresponding file
for Cortex-A78AE, causing the FVP to hang when executing the
plat_reset_handler function. The file is now included to address the
problem and to allow the new CI config for Cortex-A78AE to work
properly.

Change-Id: I8dd460831b354d8ca54841d5561df40ff193ee06
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge changes I1bfa797e,I0ec7a70e into integration

* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma

Merge changes from topic "mp/feat_ras" into integration

* changes:
refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED
refactor(ras): replace RAS_EXTENSION with FEAT_RAS

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround platforms non-arm interconnect
refactor(errata_abi): factor in non-arm interconnect
feat(errata_abi): errata management firmware interface

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fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED

At the moment we only support FEAT_RAS to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime det

refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED

At the moment we only support FEAT_RAS to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (FEAT_RAS=2), by splitting
is_armv8_2_feat_ras_present() into an ID register reading function and
a second function to report the support status. That function considers
both build time settings and runtime information (if needed), and is
used before we access RAS related registers.

Also move the context saving code from assembly to C, and use the new
is_feat_ras_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic
option (=2), so the right decision can be made by the code at runtime.

Change-Id: I30498f72fd80b136850856244687400456a03d0e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firm

refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firmware first
handling(FFH) of RAS errors.
2. Manage the FEAT_RAS extension when switching the worlds.

FFH means that all the EAs from NS are trapped in EL3 first and signaled
to NS world later after the first handling is done in firmware. There is
an alternate way of handling RAS errors viz Kernel First handling(KFH).
Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the
feature is needed for proper handling KFH in as well.

This patch breaks down the RAS_EXTENSION flag into a flag to denote the
CPU architecture `ENABLE_FEAT_RAS` which is used in context management
during world switch and another flag `RAS_FFH_SUPPORT` to pull in
required framework and platform hooks for FFH.

Proper support for KFH will be added in future patches.

BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The
equivalent functionality can be achieved by the following
2 options:
- ENABLE_FEAT_RAS
- RAS_FFH_SUPPORT

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec

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Merge "feat(fvp): introduce PLATFORM_TEST_RAS_FFH config" into integration

feat(fvp): enable errata management interface

Errata ABI feature specific build flag, flag to enable
CPUs in the cpu list, flags to test non-arm interconnect based
errata flags when enabled from a p

feat(fvp): enable errata management interface

Errata ABI feature specific build flag, flag to enable
CPUs in the cpu list, flags to test non-arm interconnect based
errata flags when enabled from a platform level.
Added to the FVP platform makefile to test the errata abi feature
implementation.

The flags to enable CPUs in the cpu list will be removed once
synchronized with the errata framework.

Change-Id: I30877a22ac1348906a6ddfb26f9e8839912d3572
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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feat(fvp): introduce PLATFORM_TEST_RAS_FFH config

While doing RAS related tests there were few patches related with
fault injection and handling were applied through CI hooks.
These patches were inv

feat(fvp): introduce PLATFORM_TEST_RAS_FFH config

While doing RAS related tests there were few patches related with
fault injection and handling were applied through CI hooks.
These patches were invisible as they were applied and removed after the
build is done.

This patch introduces build macro PLATFORM_TEST_RAS_FFH and moves the
patches applied through CI under this.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iddba52f3ebf21f575a473e50c607a944391156b9

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