1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 84 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 85 this file name will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 98 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 99 this file name will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 105 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 106 this file name will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 184 registers in cpu context. This must be enabled, if the platform wants to use 185 this feature in the Secure world and MTE is enabled at ELX. This flag can 186 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 187 Default value is 0. 188 189- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 190 registers to be saved/restored when entering/exiting an EL2 execution 191 context. This flag can take values 0 to 2, to align with the 192 ``FEATURE_DETECTION`` mechanism. Default value is 0. 193 194- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 195 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 196 to be included when saving and restoring the CPU context as part of world 197 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 198 mechanism. Default value is 0. 199 200 Note that Pointer Authentication is enabled for Non-secure world irrespective 201 of the value of this flag if the CPU supports it. 202 203- ``DEBUG``: Chooses between a debug and release build. It can take either 0 204 (release) or 1 (debug) as values. 0 is the default. 205 206- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 207 authenticated decryption algorithm to be used to decrypt firmware/s during 208 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 209 this flag is ``none`` to disable firmware decryption which is an optional 210 feature as per TBBR. 211 212- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 213 of the binary image. If set to 1, then only the ELF image is built. 214 0 is the default. 215 216- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 217 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 218 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 219 mechanism. Default is ``0``. 220 221- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 222 Board Boot authentication at runtime. This option is meant to be enabled only 223 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 224 flag has to be enabled. 0 is the default. 225 226- ``E``: Boolean option to make warnings into errors. Default is 1. 227 228 When specifying higher warnings levels (``W=1`` and higher), this option 229 defaults to 0. This is done to encourage contributors to use them, as they 230 are expected to produce warnings that would otherwise fail the build. New 231 contributions are still expected to build with ``W=0`` and ``E=1`` (the 232 default). 233 234- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 235 the normal boot flow. It must specify the entry point address of the EL3 236 payload. Please refer to the "Booting an EL3 payload" section for more 237 details. 238 239- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 240 (also known as group 1 counters). These are implementation-defined counters, 241 and as such require additional platform configuration. Default is 0. 242 243- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 244 allows platforms with auxiliary counters to describe them via the 245 ``HW_CONFIG`` device tree blob. Default is 0. 246 247- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 248 are compiled out. For debug builds, this option defaults to 1, and calls to 249 ``assert()`` are left in place. For release builds, this option defaults to 0 250 and calls to ``assert()`` function are compiled out. This option can be set 251 independently of ``DEBUG``. It can also be used to hide any auxiliary code 252 that is only required for the assertion and does not fit in the assertion 253 itself. 254 255- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 256 dumps or not. It is supported in both AArch64 and AArch32. However, in 257 AArch32 the format of the frame records are not defined in the AAPCS and they 258 are defined by the implementation. This implementation of backtrace only 259 supports the format used by GCC when T32 interworking is disabled. For this 260 reason enabling this option in AArch32 will force the compiler to only 261 generate A32 code. This option is enabled by default only in AArch64 debug 262 builds, but this behaviour can be overridden in each platform's Makefile or 263 in the build command line. 264 265- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 266 extensions. This flag can take the values 0 to 2, to align with the 267 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 268 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 269 and this option can be used to enable this feature on those systems as well. 270 This flag can take the values 0 to 2, the default is 0. 271 272- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 273 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 274 onwards. This flag can take the values 0 to 2, to align with the 275 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 276 277- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 278 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 279 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 280 optional feature available on Arm v8.0 onwards. This flag can take values 281 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 282 Default value is ``0``. 283 284- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 285 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 286 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 287 and upwards. This flag can take the values 0 to 2, to align with the 288 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 289 290- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 291 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 292 Physical Offset register) during EL2 to EL3 context save/restore operations. 293 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 294 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 295 mechanism. Default value is ``0``. 296 297- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 298 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 299 Read Trap Register) during EL2 to EL3 context save/restore operations. 300 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 301 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 302 mechanism. Default value is ``0``. 303 304- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 305 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 306 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 307 mandatory architectural feature and is enabled from v8.7 and upwards. This 308 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 309 mechanism. Default value is ``0``. 310 311- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for 312 ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to 313 memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural 314 feature available from v8.9 and upwards. This flag can take the values 0 to 315 2, to align with the ``FEATURE_DETECTION`` mechanism. Default value is 316 ``0``. 317 318- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 319 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 320 permission fault for any privileged data access from EL1/EL2 to virtual 321 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 322 mandatory architectural feature and is enabled from v8.1 and upwards. This 323 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 324 mechanism. Default value is ``0``. 325 326- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 327 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 328 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 329 mechanism. Default value is ``0``. 330 331- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 332 extension. This feature is only supported in AArch64 state. This flag can 333 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 334 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 335 Armv8.5 onwards. 336 337- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 338 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 339 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 340 later CPUs. It is enabled from v8.5 and upwards and if needed can be 341 overidden from platforms explicitly. 342 343- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 344 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 345 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 346 mechanism. Default is ``0``. 347 348- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 349 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 350 available on Arm v8.6. This flag can take values 0 to 2, to align with the 351 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 352 353 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 354 delayed by the amount of value in ``TWED_DELAY``. 355 356- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 357 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 358 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 359 architectural feature and is enabled from v8.1 and upwards. It can take 360 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 361 Default value is ``0``. 362 363- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 364 allow access to TCR2_EL2 (extended translation control) from EL2 as 365 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 366 mandatory architectural feature and is enabled from v8.9 and upwards. This 367 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 368 mechanism. Default value is ``0``. 369 370- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 371 at EL2 and below, and context switch relevant registers. This flag 372 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 373 mechanism. Default value is ``0``. 374 375- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 376 at EL2 and below, and context switch relevant registers. This flag 377 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 378 mechanism. Default value is ``0``. 379 380- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 381 at EL2 and below, and context switch relevant registers. This flag 382 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 383 mechanism. Default value is ``0``. 384 385- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 386 at EL2 and below, and context switch relevant registers. This flag 387 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 388 mechanism. Default value is ``0``. 389 390- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 391 allow use of Guarded Control Stack from EL2 as well as adding the GCS 392 registers to the EL2 context save/restore operations. This flag can take 393 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 394 Default value is ``0``. 395 396- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 397 support in GCC for TF-A. This option is currently only supported for 398 AArch64. Default is 0. 399 400- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM 401 feature. MPAM is an optional Armv8.4 extension that enables various memory 402 system components and resources to define partitions; software running at 403 various ELs can assign themselves to desired partition to control their 404 performance aspects. 405 406 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 407 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 408 access their own MPAM registers without trapping into EL3. This option 409 doesn't make use of partitioning in EL3, however. Platform initialisation 410 code should configure and use partitions in EL3 as required. This option 411 defaults to ``0``. 412 413- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 414 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 415 firmware to detect and limit high activity events to assist in SoC processor 416 power domain dynamic power budgeting and limit the triggering of whole-rail 417 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 418 419- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 420 allows platforms with cores supporting MPMM to describe them via the 421 ``HW_CONFIG`` device tree blob. Default is 0. 422 423- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 424 support within generic code in TF-A. This option is currently only supported 425 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 426 in BL32 (SP_min) for AARCH32. Default is 0. 427 428- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 429 Measurement Framework(PMF). Default is 0. 430 431- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 432 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 433 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 434 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 435 software. 436 437- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 438 Management Extension. This flag can take the values 0 to 2, to align with 439 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 440 an experimental feature. 441 442- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 443 instrumentation which injects timestamp collection points into TF-A to 444 allow runtime performance to be measured. Currently, only PSCI is 445 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 446 as well. Default is 0. 447 448- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 449 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 450 registers so are enabled together. Using this option without 451 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 452 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 453 superset of SVE. SME is an optional architectural feature for AArch64 454 and TF-A support is experimental. At this time, this build option cannot be 455 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to 456 build with these options will fail. This flag can take the values 0 to 2, to 457 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 458 459- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 460 version 2 (SME2) for the non-secure world only. SME2 is an optional 461 architectural feature for AArch64 and TF-A support is experimental. 462 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 463 accesses will still be trapped. This flag can take the values 0 to 2, to 464 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 465 466- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 467 Extension for secure world. Used along with SVE and FPU/SIMD. 468 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 469 This is experimental. Default is 0. 470 471- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 472 extensions. This is an optional architectural feature for AArch64. 473 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 474 mechanism. The default is 2 but is automatically disabled when the target 475 architecture is AArch32. 476 477- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 478 (SVE) for the Non-secure world only. SVE is an optional architectural feature 479 for AArch64. Note that when SVE is enabled for the Non-secure world, access 480 to SIMD and floating-point functionality from the Secure world is disabled by 481 default and controlled with ENABLE_SVE_FOR_SWD. 482 This is to avoid corruption of the Non-secure world data in the Z-registers 483 which are aliased by the SIMD and FP registers. The build option is not 484 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 485 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 486 enabled. This flag can take the values 0 to 2, to align with the 487 ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be 488 used on systems that have SPM_MM enabled. The default is 1. 489 490- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 491 SVE is an optional architectural feature for AArch64. Note that this option 492 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 493 automatically disabled when the target architecture is AArch32. 494 495- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 496 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 497 default value is set to "none". "strong" is the recommended stack protection 498 level if this feature is desired. "none" disables the stack protection. For 499 all values other than "none", the ``plat_get_stack_protector_canary()`` 500 platform hook needs to be implemented. The value is passed as the last 501 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 502 503- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 504 flag depends on ``DECRYPTION_SUPPORT`` build flag. 505 506- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 507 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 508 509- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 510 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 511 on ``DECRYPTION_SUPPORT`` build flag. 512 513- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 514 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 515 build flag. 516 517- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 518 deprecated platform APIs, helper functions or drivers within Trusted 519 Firmware as error. It can take the value 1 (flag the use of deprecated 520 APIs as error) or 0. The default is 0. 521 522- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 523 targeted at EL3. When set ``0`` (default), no exceptions are expected or 524 handled at EL3, and a panic will result. The exception to this rule is when 525 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 526 occuring during normal world execution, are trapped to EL3. Any exception 527 trapped during secure world execution are trapped to the SPMC. This is 528 supported only for AArch64 builds. 529 530- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 531 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 532 Default value is 40 (LOG_LEVEL_INFO). 533 534- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 535 injection from lower ELs, and this build option enables lower ELs to use 536 Error Records accessed via System Registers to inject faults. This is 537 applicable only to AArch64 builds. 538 539 This feature is intended for testing purposes only, and is advisable to keep 540 disabled for production images. 541 542- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 543 detection mechanism. It detects whether the Architectural features enabled 544 through feature specific build flags are supported by the PE or not by 545 validating them either at boot phase or at runtime based on the value 546 possessed by the feature flag (0 to 2) and report error messages at an early 547 stage. This flag will also enable errata ordering checking for ``DEBUG`` 548 builds. 549 550 This prevents and benefits us from EL3 runtime exceptions during context save 551 and restore routines guarded by these build flags. Henceforth validating them 552 before their usage provides more control on the actions taken under them. 553 554 The mechanism permits the build flags to take values 0, 1 or 2 and 555 evaluates them accordingly. 556 557 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 558 559 :: 560 561 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 562 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 563 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 564 565 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 566 0, feature is disabled statically during compilation. If it is defined as 1, 567 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 568 implemented by the PE, a hard panic is generated. Finally, if the flag is set 569 to 2, feature is validated at runtime. 570 571 Note that the entire implementation is divided into two phases, wherein as 572 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 573 supported and is planned to be handled explicilty in phase-2 implementation. 574 575 FEATURE_DETECTION macro is disabled by default, and is currently an 576 experimental procedure. Platforms can explicitly make use of this by 577 mechanism, by enabling it to validate whether they have set their build flags 578 properly at an early phase. 579 580- ``FIP_NAME``: This is an optional build option which specifies the FIP 581 filename for the ``fip`` target. Default is ``fip.bin``. 582 583- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 584 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 585 586- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 587 588 :: 589 590 0: Encryption is done with Secret Symmetric Key (SSK) which is common 591 for a class of devices. 592 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 593 unique per device. 594 595 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 596 597- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 598 tool to create certificates as per the Chain of Trust described in 599 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 600 include the certificates in the FIP and FWU_FIP. Default value is '0'. 601 602 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 603 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 604 the corresponding certificates, and to include those certificates in the 605 FIP and FWU_FIP. 606 607 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 608 images will not include support for Trusted Board Boot. The FIP will still 609 include the corresponding certificates. This FIP can be used to verify the 610 Chain of Trust on the host machine through other mechanisms. 611 612 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 613 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 614 will not include the corresponding certificates, causing a boot failure. 615 616- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 617 inherent support for specific EL3 type interrupts. Setting this build option 618 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 619 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 620 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 621 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 622 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 623 the Secure Payload interrupts needs to be synchronously handed over to Secure 624 EL1 for handling. The default value of this option is ``0``, which means the 625 Group 0 interrupts are assumed to be handled by Secure EL1. 626 627- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 628 Interrupts, resulting from errors in NS world, will be always trapped in 629 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 630 will be trapped in the current exception level (or in EL1 if the current 631 exception level is EL0). 632 633- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 634 software operations are required for CPUs to enter and exit coherency. 635 However, newer systems exist where CPUs' entry to and exit from coherency 636 is managed in hardware. Such systems require software to only initiate these 637 operations, and the rest is managed in hardware, minimizing active software 638 management. In such systems, this boolean option enables TF-A to carry out 639 build and run-time optimizations during boot and power management operations. 640 This option defaults to 0 and if it is enabled, then it implies 641 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 642 643 If this flag is disabled while the platform which TF-A is compiled for 644 includes cores that manage coherency in hardware, then a compilation error is 645 generated. This is based on the fact that a system cannot have, at the same 646 time, cores that manage coherency in hardware and cores that don't. In other 647 words, a platform cannot have, at the same time, cores that require 648 ``HW_ASSISTED_COHERENCY=1`` and cores that require 649 ``HW_ASSISTED_COHERENCY=0``. 650 651 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 652 translation library (xlat tables v2) must be used; version 1 of translation 653 library is not supported. 654 655- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 656 implementation defined system register accesses from lower ELs. Default 657 value is ``0``. 658 659- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 660 bottom, higher addresses at the top. This build flag can be set to '1' to 661 invert this behavior. Lower addresses will be printed at the top and higher 662 addresses at the bottom. 663 664- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 665 used for generating the PKCS keys and subsequent signing of the certificate. 666 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 667 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 668 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 669 compatibility. The default value of this flag is ``rsa`` which is the TBBR 670 compliant PKCS#1 RSA 2.1 scheme. 671 672- ``KEY_SIZE``: This build flag enables the user to select the key size for 673 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 674 depend on the chosen algorithm and the cryptographic module. 675 676 +---------------------------+------------------------------------+ 677 | KEY_ALG | Possible key sizes | 678 +===========================+====================================+ 679 | rsa | 1024 , 2048 (default), 3072, 4096* | 680 +---------------------------+------------------------------------+ 681 | ecdsa | unavailable | 682 +---------------------------+------------------------------------+ 683 | ecdsa-brainpool-regular | unavailable | 684 +---------------------------+------------------------------------+ 685 | ecdsa-brainpool-twisted | unavailable | 686 +---------------------------+------------------------------------+ 687 688 689 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 690 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 691 692- ``HASH_ALG``: This build flag enables the user to select the secure hash 693 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 694 The default value of this flag is ``sha256``. 695 696- ``LDFLAGS``: Extra user options appended to the linkers' command line in 697 addition to the one set by the build system. 698 699- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 700 output compiled into the build. This should be one of the following: 701 702 :: 703 704 0 (LOG_LEVEL_NONE) 705 10 (LOG_LEVEL_ERROR) 706 20 (LOG_LEVEL_NOTICE) 707 30 (LOG_LEVEL_WARNING) 708 40 (LOG_LEVEL_INFO) 709 50 (LOG_LEVEL_VERBOSE) 710 711 All log output up to and including the selected log level is compiled into 712 the build. The default value is 40 in debug builds and 20 in release builds. 713 714- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 715 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 716 provide trust that the code taking the measurements and recording them has 717 not been tampered with. 718 719 This option defaults to 0. 720 721- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 722 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 723 the measurements and recording them as per `PSA DRTM specification`_. For 724 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 725 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 726 should have mechanism to authenticate BL31. This is an experimental feature. 727 728 This option defaults to 0. 729 730- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 731 specifies the file that contains the Non-Trusted World private key in PEM 732 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 733 734- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 735 optional. It is only needed if the platform makefile specifies that it 736 is required in order to build the ``fwu_fip`` target. 737 738- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 739 contents upon world switch. It can take either 0 (don't save and restore) or 740 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 741 wants the timer registers to be saved and restored. 742 743- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in 744 tb_fw_config device tree. This flag is defined only when 745 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp. 746 747- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 748 for the BL image. It can be either 0 (include) or 1 (remove). The default 749 value is 0. 750 751- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 752 the underlying hardware is not a full PL011 UART but a minimally compliant 753 generic UART, which is a subset of the PL011. The driver will not access 754 any register that is not part of the SBSA generic UART specification. 755 Default value is 0 (a full PL011 compliant UART is present). 756 757- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 758 must be subdirectory of any depth under ``plat/``, and must contain a 759 platform makefile named ``platform.mk``. For example, to build TF-A for the 760 Arm Juno board, select PLAT=juno. 761 762- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 763 instead of the normal boot flow. When defined, it must specify the entry 764 point address for the preloaded BL33 image. This option is incompatible with 765 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 766 over ``PRELOADED_BL33_BASE``. 767 768- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 769 vector address can be programmed or is fixed on the platform. It can take 770 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 771 programmable reset address, it is expected that a CPU will start executing 772 code directly at the right address, both on a cold and warm reset. In this 773 case, there is no need to identify the entrypoint on boot and the boot path 774 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 775 does not need to be implemented in this case. 776 777- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 778 possible for the PSCI power-state parameter: original and extended State-ID 779 formats. This flag if set to 1, configures the generic PSCI layer to use the 780 extended format. The default value of this flag is 0, which means by default 781 the original power-state format is used by the PSCI implementation. This flag 782 should be specified by the platform makefile and it governs the return value 783 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 784 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 785 set to 1 as well. 786 787- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 788 OS-initiated mode. This option defaults to 0. 789 790- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features 791 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 792 or later CPUs. This flag can take the values 0 to 2, to align with the 793 ``FEATURE_DETECTION`` mechanism. 794 795- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors 796 originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``, 797 ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``. 798 799- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 800 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 801 entrypoint) or 1 (CPU reset to BL31 entrypoint). 802 The default value is 0. 803 804- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 805 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 806 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 807 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 808 809- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 810 file that contains the ROT private key in PEM format and enforces public key 811 hash generation. If ``SAVE_KEYS=1``, this 812 file name will be used to save the key. 813 814- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 815 certificate generation tool to save the keys used to establish the Chain of 816 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 817 818- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 819 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 820 target. 821 822- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 823 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 824 this file name will be used to save the key. 825 826- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 827 optional. It is only needed if the platform makefile specifies that it 828 is required in order to build the ``fwu_fip`` target. 829 830- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 831 Delegated Exception Interface to BL31 image. This defaults to ``0``. 832 833 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 834 set to ``1``. 835 836- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 837 isolated on separate memory pages. This is a trade-off between security and 838 memory usage. See "Isolating code and read-only data on separate memory 839 pages" section in :ref:`Firmware Design`. This flag is disabled by default 840 and affects all BL images. 841 842- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 843 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 844 allocated in RAM discontiguous from the loaded firmware image. When set, the 845 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 846 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 847 sections are placed in RAM immediately following the loaded firmware image. 848 849- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 850 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 851 discontiguous from loaded firmware images. When set, the platform need to 852 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 853 flag is disabled by default and NOLOAD sections are placed in RAM immediately 854 following the loaded firmware image. 855 856- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 857 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 858 UEFI+ACPI this can provide a certain amount of OS forward compatibility 859 with newer platforms that aren't ECAM compliant. 860 861- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 862 This build option is only valid if ``ARCH=aarch64``. The value should be 863 the path to the directory containing the SPD source, relative to 864 ``services/spd/``; the directory is expected to contain a makefile called 865 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 866 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 867 cannot be enabled when the ``SPM_MM`` option is enabled. 868 869- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 870 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 871 execution in BL1 just before handing over to BL31. At this point, all 872 firmware images have been loaded in memory, and the MMU and caches are 873 turned off. Refer to the "Debugging options" section for more details. 874 875- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 876 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 877 component runs at the EL3 exception level. The default value is ``0`` ( 878 disabled). This configuration supports pre-Armv8.4 platforms (aka not 879 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 880 881- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 882 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 883 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 884 mechanism should be used. 885 886- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 887 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 888 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 889 extension. This is the default when enabling the SPM Dispatcher. When 890 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 891 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 892 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 893 extension). 894 895- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 896 Partition Manager (SPM) implementation. The default value is ``0`` 897 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 898 enabled (``SPD=spmd``). 899 900- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 901 description of secure partitions. The build system will parse this file and 902 package all secure partition blobs into the FIP. This file is not 903 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 904 905- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 906 secure interrupts (caught through the FIQ line). Platforms can enable 907 this directive if they need to handle such interruption. When enabled, 908 the FIQ are handled in monitor mode and non secure world is not allowed 909 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 910 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 911 912- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 913 Platforms can configure this if they need to lower the hardware 914 limit, for example due to asymmetric configuration or limitations of 915 software run at lower ELs. The default is the architectural maximum 916 of 2048 which should be suitable for most configurations, the 917 hardware will limit the effective VL to the maximum physically supported 918 VL. 919 920- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 921 Random Number Generator Interface to BL31 image. This defaults to ``0``. 922 923- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 924 Boot feature. When set to '1', BL1 and BL2 images include support to load 925 and verify the certificates and images in a FIP, and BL1 includes support 926 for the Firmware Update. The default value is '0'. Generation and inclusion 927 of certificates in the FIP and FWU_FIP depends upon the value of the 928 ``GENERATE_COT`` option. 929 930 .. warning:: 931 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 932 already exist in disk, they will be overwritten without further notice. 933 934- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 935 specifies the file that contains the Trusted World private key in PEM 936 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 937 938- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 939 synchronous, (see "Initializing a BL32 Image" section in 940 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 941 synchronous method) or 1 (BL32 is initialized using asynchronous method). 942 Default is 0. 943 944- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 945 routing model which routes non-secure interrupts asynchronously from TSP 946 to EL3 causing immediate preemption of TSP. The EL3 is responsible 947 for saving and restoring the TSP context in this routing model. The 948 default routing model (when the value is 0) is to route non-secure 949 interrupts to TSP allowing it to save its context and hand over 950 synchronously to EL3 via an SMC. 951 952 .. note:: 953 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 954 must also be set to ``1``. 955 956- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 957 internal-trusted-storage) as SP in tb_fw_config device tree. 958 959- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 960 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 961 this delay. It can take values in the range (0-15). Default value is ``0`` 962 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 963 Platforms need to explicitly update this value based on their requirements. 964 965- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 966 linker. When the ``LINKER`` build variable points to the armlink linker, 967 this flag is enabled automatically. To enable support for armlink, platforms 968 will have to provide a scatter file for the BL image. Currently, Tegra 969 platforms use the armlink support to compile BL3-1 images. 970 971- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 972 memory region in the BL memory map or not (see "Use of Coherent memory in 973 TF-A" section in :ref:`Firmware Design`). It can take the value 1 974 (Coherent memory region is included) or 0 (Coherent memory region is 975 excluded). Default is 1. 976 977- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 978 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 979 Default is 0. 980 981- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 982 firmware configuration framework. This will move the io_policies into a 983 configuration device tree, instead of static structure in the code base. 984 985- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 986 at runtime using fconf. If this flag is enabled, COT descriptors are 987 statically captured in tb_fw_config file in the form of device tree nodes 988 and properties. Currently, COT descriptors used by BL2 are moved to the 989 device tree and COT descriptors used by BL1 are retained in the code 990 base statically. 991 992- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 993 runtime using firmware configuration framework. The platform specific SDEI 994 shared and private events configuration is retrieved from device tree rather 995 than static C structures at compile time. This is only supported if 996 SDEI_SUPPORT build flag is enabled. 997 998- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 999 and Group1 secure interrupts using the firmware configuration framework. The 1000 platform specific secure interrupt property descriptor is retrieved from 1001 device tree in runtime rather than depending on static C structure at compile 1002 time. 1003 1004- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1005 This feature creates a library of functions to be placed in ROM and thus 1006 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1007 is 0. 1008 1009- ``V``: Verbose build. If assigned anything other than 0, the build commands 1010 are printed. Default is 0. 1011 1012- ``VERSION_STRING``: String used in the log output for each TF-A image. 1013 Defaults to a string formed by concatenating the version number, build type 1014 and build string. 1015 1016- ``W``: Warning level. Some compiler warning options of interest have been 1017 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1018 each level enabling more warning options. Default is 0. 1019 1020 This option is closely related to the ``E`` option, which enables 1021 ``-Werror``. 1022 1023 - ``W=0`` (default) 1024 1025 Enables a wide assortment of warnings, most notably ``-Wall`` and 1026 ``-Wextra``, as well as various bad practices and things that are likely to 1027 result in errors. Includes some compiler specific flags. No warnings are 1028 expected at this level for any build. 1029 1030 - ``W=1`` 1031 1032 Enables warnings we want the generic build to include but are too time 1033 consuming to fix at the moment. It re-enables warnings taken out for 1034 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1035 to eventually be merged into ``W=0``. Some warnings are expected on some 1036 builds, but new contributions should not introduce new ones. 1037 1038 - ``W=2`` (recommended) 1039 1040 Enables warnings we want the generic build to include but cannot be enabled 1041 due to external libraries. This level is expected to eventually be merged 1042 into ``W=0``. Lots of warnings are expected, primarily from external 1043 libraries like zlib and compiler-rt, but new controbutions should not 1044 introduce new ones. 1045 1046 - ``W=3`` 1047 1048 Enables warnings that are informative but not necessary and generally too 1049 verbose and frequently ignored. A very large number of warnings are 1050 expected. 1051 1052 The exact set of warning flags depends on the compiler and TF-A warning 1053 level, however they are all succinctly set in the top-level Makefile. Please 1054 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1055 individual flags. 1056 1057- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1058 the CPU after warm boot. This is applicable for platforms which do not 1059 require interconnect programming to enable cache coherency (eg: single 1060 cluster platforms). If this option is enabled, then warm boot path 1061 enables D-caches immediately after enabling MMU. This option defaults to 0. 1062 1063- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1064 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1065 default value of this flag is ``no``. Note this option must be enabled only 1066 for ARM architecture greater than Armv8.5-A. 1067 1068- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1069 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1070 The default value of this flag is ``0``. 1071 1072 ``AT`` speculative errata workaround disables stage1 page table walk for 1073 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1074 produces either the correct result or failure without TLB allocation. 1075 1076 This boolean option enables errata for all below CPUs. 1077 1078 +---------+--------------+-------------------------+ 1079 | Errata | CPU | Workaround Define | 1080 +=========+==============+=========================+ 1081 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1082 +---------+--------------+-------------------------+ 1083 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1084 +---------+--------------+-------------------------+ 1085 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1086 +---------+--------------+-------------------------+ 1087 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1088 +---------+--------------+-------------------------+ 1089 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1090 +---------+--------------+-------------------------+ 1091 1092 .. note:: 1093 This option is enabled by build only if platform sets any of above defines 1094 mentioned in ’Workaround Define' column in the table. 1095 If this option is enabled for the EL3 software then EL2 software also must 1096 implement this workaround due to the behaviour of the errata mentioned 1097 in new SDEN document which will get published soon. 1098 1099- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1100 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1101 This flag is disabled by default. 1102 1103- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1104 host machine where a custom installation of OpenSSL is located, which is used 1105 to build the certificate generation, firmware encryption and FIP tools. If 1106 this option is not set, the default OS installation will be used. 1107 1108- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1109 functions that wait for an arbitrary time length (udelay and mdelay). The 1110 default value is 0. 1111 1112- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1113 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1114 optional architectural feature for AArch64. This flag can take the values 1115 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1116 and it is automatically disabled when the target architecture is AArch32. 1117 1118- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1119 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1120 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1121 feature for AArch64. This flag can take the values 0 to 2, to align with the 1122 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1123 disabled when the target architecture is AArch32. 1124 1125- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1126 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1127 but unused). This feature is available if trace unit such as ETMv4.x, and 1128 ETE(extending ETM feature) is implemented. This flag can take the values 1129 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1130 1131- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1132 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1133 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1134 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1135 1136- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA 1137 APIs on platforms that doesn't support RSS (providing Arm CCA HES 1138 functionalities). When enabled (``1``), a mocked version of the APIs are used. 1139 The default value is 0. 1140 1141- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1142 ``plat_can_cmo`` which will return zero if cache management operations should 1143 be skipped and non-zero otherwise. By default, this option is disabled which 1144 means platform hook won't be checked and CMOs will always be performed when 1145 related functions are called. 1146 1147- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1148 firmware interface for the BL31 image. By default its disabled (``0``). 1149 1150- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1151 errata mitigation for platforms with a non-arm interconnect using the errata 1152 ABI. By default its disabled (``0``). 1153 1154GICv3 driver options 1155-------------------- 1156 1157GICv3 driver files are included using directive: 1158 1159``include drivers/arm/gic/v3/gicv3.mk`` 1160 1161The driver can be configured with the following options set in the platform 1162makefile: 1163 1164- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1165 Enabling this option will add runtime detection support for the 1166 GIC-600, so is safe to select even for a GIC500 implementation. 1167 This option defaults to 0. 1168 1169- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1170 for GIC-600 AE. Enabling this option will introduce support to initialize 1171 the FMU. Platforms should call the init function during boot to enable the 1172 FMU and its safety mechanisms. This option defaults to 0. 1173 1174- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1175 functionality. This option defaults to 0 1176 1177- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1178 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1179 functions. This is required for FVP platform which need to simulate GIC save 1180 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1181 1182- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1183 This option defaults to 0. 1184 1185- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1186 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1187 1188Debugging options 1189----------------- 1190 1191To compile a debug version and make the build more verbose use 1192 1193.. code:: shell 1194 1195 make PLAT=<platform> DEBUG=1 V=1 all 1196 1197AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1198(for example Arm-DS) might not support this and may need an older version of 1199DWARF symbols to be emitted by GCC. This can be achieved by using the 1200``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1201the version to 4 is recommended for Arm-DS. 1202 1203When debugging logic problems it might also be useful to disable all compiler 1204optimizations by using ``-O0``. 1205 1206.. warning:: 1207 Using ``-O0`` could cause output images to be larger and base addresses 1208 might need to be recalculated (see the **Memory layout on Arm development 1209 platforms** section in the :ref:`Firmware Design`). 1210 1211Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1212``LDFLAGS``: 1213 1214.. code:: shell 1215 1216 CFLAGS='-O0 -gdwarf-2' \ 1217 make PLAT=<platform> DEBUG=1 V=1 all 1218 1219Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1220ignored as the linker is called directly. 1221 1222It is also possible to introduce an infinite loop to help in debugging the 1223post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1224``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1225section. In this case, the developer may take control of the target using a 1226debugger when indicated by the console output. When using Arm-DS, the following 1227commands can be used: 1228 1229:: 1230 1231 # Stop target execution 1232 interrupt 1233 1234 # 1235 # Prepare your debugging environment, e.g. set breakpoints 1236 # 1237 1238 # Jump over the debug loop 1239 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1240 1241 # Resume execution 1242 continue 1243 1244Firmware update options 1245----------------------- 1246 1247- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1248 in defining the firmware update metadata structure. This flag is by default 1249 set to '2'. 1250 1251- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1252 firmware bank. Each firmware bank must have the same number of images as per 1253 the `PSA FW update specification`_. 1254 This flag is used in defining the firmware update metadata structure. This 1255 flag is by default set to '1'. 1256 1257- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1258 `PSA FW update specification`_. The default value is 0, and this is an 1259 experimental feature. 1260 PSA firmware update implementation has some limitations, such as BL2 is 1261 not part of the protocol-updatable images, if BL2 needs to be updated, then 1262 it should be done through another platform-defined mechanism, and it assumes 1263 that the platform's hardware supports CRC32 instructions. 1264 1265-------------- 1266 1267*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1268 1269.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1270.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1271.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1272.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1273.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1274