1 /* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_features.h> 9 #include <arch_helpers.h> 10 #include <lib/el3_runtime/pubsub.h> 11 #include <lib/extensions/trbe.h> 12 13 static void tsb_csync(void) 14 { 15 /* 16 * The assembler does not yet understand the tsb csync mnemonic 17 * so use the equivalent hint instruction. 18 */ 19 __asm__ volatile("hint #18"); 20 } 21 22 void trbe_init_el3(void) 23 { 24 u_register_t val; 25 26 /* 27 * MDCR_EL3.NSTB = 0b11 28 * Allow access of trace buffer control registers from NS-EL1 29 * and NS-EL2, tracing is prohibited in Secure and Realm state 30 * (if implemented). 31 */ 32 val = read_mdcr_el3(); 33 val |= MDCR_NSTB(MDCR_NSTB_EL1); 34 write_mdcr_el3(val); 35 } 36 37 void trbe_init_el2_unused(void) 38 { 39 /* 40 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 41 * owning exception level is NS-EL1 and, tracing is 42 * prohibited at NS-EL2. These bits are RES0 when 43 * FEAT_TRBE is not implemented. 44 */ 45 write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 46 } 47 48 static void *trbe_drain_trace_buffers_hook(const void *arg __unused) 49 { 50 if (is_feat_trbe_supported()) { 51 /* 52 * Before switching from normal world to secure world 53 * the trace buffers need to be drained out to memory. This is 54 * required to avoid an invalid memory access when TTBR is switched 55 * for entry to S-EL1. 56 */ 57 tsb_csync(); 58 dsbnsh(); 59 } 60 61 return (void *)0; 62 } 63 64 SUBSCRIBE_TO_EVENT(cm_entering_secure_world, trbe_drain_trace_buffers_hook); 65