| #
b50c7af1 |
| 11-Dec-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "hm/evlog" into integration
* changes:
refactor(drtm): use crypto-agile measured boot
refactor(imx): use crypto-agile measured boot
refactor(qemu): use crypto-agile me
Merge changes from topic "hm/evlog" into integration
* changes:
refactor(drtm): use crypto-agile measured boot
refactor(imx): use crypto-agile measured boot
refactor(qemu): use crypto-agile measured boot
refactor(juno): use crypto-agile measured boot
refactor(rpi3): use crypto-agile measured boot
refactor(fvp): use crypto-agile measured boot
feat(measured-boot): enable dynamic hash provisioning
feat: add TPM/TCG hashing helper to crypto module
chore: bump event log library
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|
| #
8a583b97 |
| 07-Oct-2025 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(fvp): use crypto-agile measured boot
Update the FVP measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection
refactor(fvp): use crypto-agile measured boot
Update the FVP measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.
Change-Id: I4128a0c66a56df6c473c47a577d86cd38bf057f6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| #
0390a0b2 |
| 08-Dec-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(fvp): load SP_PKGs with TRANSFER_LIST" into integration
|
| #
6ae88e28 |
| 05-Sep-2025 |
Yeoreum Yun <yeoreum.yun@arm.com> |
feat(fvp): load SP_PKGs with TRANSFER_LIST
To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_trans
feat(fvp): load SP_PKGs with TRANSFER_LIST
To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_transfer_list_dyn_cfg_init().
Since there is no standard tag_id defined for TB_FW_CONFIG in the
transfer list, define PLAT_ARM_TB_FW_CONFIG_TL_TAG as a platform-specific
identifier to load TB_FW_CONFIG.
With this change, BL2 can load the SP_PKGs specified in TB_FW_CONFIG.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I2470c1ef3bf2bf921d0de1fff541565df13eaee4
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| #
fd2fb5b7 |
| 04-Dec-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "ar/feat_uinj" into integration
* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): u
Merge changes from topic "ar/feat_uinj" into integration
* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): update feature names and comments
fix(cpufeat): simplify AArch32 feature disablement
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|
| #
02b22a5a |
| 01-Dec-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "tc-lsc-25-cpu-libs" into integration
* changes:
feat(cpus): add support for LSC25 E-core CPU
feat(cpus): add support for LSC25 P-core CPU
|
| #
4286d16f |
| 26-Nov-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(cpufeat): add support for FEAT_UINJ
FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return
feat(cpufeat): add support for FEAT_UINJ
FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).
This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b
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|
| #
bff6e602 |
| 04-Mar-2025 |
Ryan Everett <ryan.everett@arm.com> |
feat(cpus): add support for LSC25 E-core CPU
Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.
Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan
feat(cpus): add support for LSC25 E-core CPU
Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.
Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>
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|
| #
e1fbad0b |
| 04-Mar-2025 |
Ryan Everett <ryan.everett@arm.com> |
feat(cpus): add support for LSC25 P-core CPU
Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.
Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan
feat(cpus): add support for LSC25 P-core CPU
Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.
Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>
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|
| #
4e820fc4 |
| 10-Nov-2025 |
Chris Kay <chris.kay@arm.com> |
Merge "chore(fvp): bump maximum permitted Trusted SRAM size" into integration
|
| #
cfe7ff31 |
| 10-Nov-2025 |
Chris Kay <chris.kay@arm.com> |
chore(fvp): bump maximum permitted Trusted SRAM size
Bump the size of the Trusted SRAM in FVP builds, as we are now exceeding
the 256KB limit in a meaningful number of builds.
Change-Id: Iefd584172
chore(fvp): bump maximum permitted Trusted SRAM size
Bump the size of the Trusted SRAM in FVP builds, as we are now exceeding
the 256KB limit in a meaningful number of builds.
Change-Id: Iefd58417297507eaa9b24e55fc36de67bd16b716
Signed-off-by: Chris Kay <chris.kay@arm.com>
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|
| #
4ab55c2f |
| 05-Nov-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2" into integration
|
| #
714a1a93 |
| 28-Oct-2025 |
Manish Pandey <manish.pandey2@arm.com> |
fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2
Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff
fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2
Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.
This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973
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|
| #
99800361 |
| 29-Oct-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "feat(cpus): add support for venom cpu" into integration
|
| #
ab471aeb |
| 29-Oct-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(security): add clrbhb support" into integration
|
| #
d6affea1 |
| 02-Oct-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
fix(security): add clrbhb support
TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/
On platforms that support `
fix(security): add clrbhb support
TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/
On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.
Ref- https://developer.arm.com/documentation/102898/0108/
Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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|
| #
d4c50e77 |
| 14-Oct-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
feat(cpus): add support for venom cpu
Add basic CPU library code to support Venom CPU
Change-Id: I84d4cb77b175812811a17e55b4b290585e05d216
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
|
| #
ef44101e |
| 27-Oct-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "feat(cpus): add support for Dionysus cpu library" into integration
|
| #
2cdc34c5 |
| 26-Aug-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(cpus): add support for Dionysus cpu library
Add basic CPU library code to support the Dionysus CPU.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4e6b3c7e7369b7cbf0
feat(cpus): add support for Dionysus cpu library
Add basic CPU library code to support the Dionysus CPU.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4e6b3c7e7369b7cbf0e18d295e5ef5352f621e44
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|
| #
ecb8b2de |
| 16-Oct-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(cpufeat): enable FEAT_PFAR support" into integration
|
| #
b3bcfd12 |
| 14-Aug-2025 |
Andre Przywara <andre.przywara@arm.com> |
feat(cpufeat): enable FEAT_PFAR support
Implement support for FEAT_PFAR, which introduces the PFAR_ELx system
register, recording the faulting physical address for some aborts.
Those system register
feat(cpufeat): enable FEAT_PFAR support
Implement support for FEAT_PFAR, which introduces the PFAR_ELx system
register, recording the faulting physical address for some aborts.
Those system registers are trapped by the SCR_EL3.PFARen bit, so set the
bit for the non-secure world context to allow OSes to use the feature.
This is controlled by the ENABLE_FEAT_PFAR build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.
Change-Id: I5c9ae750417e75792f693732df3869e02b6e4319
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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|
| #
aa05796e |
| 15-Oct-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(cpufeat): enable FEAT_AIE support" into integration
|
| #
5c164a9f |
| 14-Oct-2025 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "gr/cpu_lib" into integration
* changes:
feat(cpus): add support for caddo cpu
feat(cpus): add support for veymont cpu
|
| #
bded41d9 |
| 14-Oct-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I769ac07f,Ia52ad5ed,I5d22ff86,Iea14d49c into integration
* changes:
fix(build): prevent races on the build directory
refactor(build): make it standard to request a custom linker sc
Merge changes I769ac07f,Ia52ad5ed,I5d22ff86,Iea14d49c into integration
* changes:
fix(build): prevent races on the build directory
refactor(build): make it standard to request a custom linker script
perf(bl32): don't call cm_get_context() unnecessarily
refactor(bl1): simplify context getting and setting
show more ...
|
| #
5be66449 |
| 08-Oct-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor(build): make it standard to request a custom linker script
Hoist the add_define to a global location so that platforms only have to
declare its usage. Fix up #ifdef to #if since we will now
refactor(build): make it standard to request a custom linker script
Hoist the add_define to a global location so that platforms only have to
declare its usage. Fix up #ifdef to #if since we will now always pass a
definition.
Change-Id: Ia52ad5ed4dcbd157d139c8ca2fb3d35b32343b93
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
show more ...
|