1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27FVP_TRUSTED_SRAM_SIZE := 384 28 29# Macro to enable helpers for running SPM tests. Disabled by default. 30PLAT_TEST_SPM := 0 31 32 33# Enable passing the DT to BL33 in x0 by default. 34USE_KERNEL_DT_CONVENTION := 1 35 36# By default dont build CPUs with no FVP model. 37BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 38 39ENABLE_FEAT_AMU := 2 40ENABLE_FEAT_AMUv1p1 := 2 41ENABLE_FEAT_HCX := 2 42ENABLE_FEAT_RNG := 2 43ENABLE_FEAT_TWED := 2 44ENABLE_FEAT_GCS := 2 45 46ifeq (${ARCH}, aarch64) 47 48ifeq (${SPM_MM}, 0) 49ifeq (${CTX_INCLUDE_FPREGS}, 0) 50 ENABLE_SME_FOR_NS := 2 51 ENABLE_SME2_FOR_NS := 2 52else 53 ENABLE_SVE_FOR_NS := 0 54 ENABLE_SME_FOR_NS := 0 55 ENABLE_SME2_FOR_NS := 0 56endif 57endif 58 59 ENABLE_BRBE_FOR_NS := 2 60 ENABLE_TRBE_FOR_NS := 2 61 ENABLE_FEAT_D128 := 2 62 ENABLE_FEAT_FPMR := 2 63 ENABLE_FEAT_MOPS := 2 64 ENABLE_FEAT_FGWTE3 := 2 65 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 66 ENABLE_FEAT_CPA2 := 2 67 ENABLE_FEAT_UINJ := 2 68endif 69 70ENABLE_SYS_REG_TRACE_FOR_NS := 2 71ENABLE_FEAT_CSV2_2 := 2 72ENABLE_FEAT_CSV2_3 := 2 73ENABLE_FEAT_CLRBHB := 2 74ENABLE_FEAT_DEBUGV8P9 := 2 75ENABLE_FEAT_DIT := 2 76ENABLE_FEAT_PAN := 2 77ENABLE_FEAT_VHE := 2 78CTX_INCLUDE_NEVE_REGS := 2 79ENABLE_FEAT_SEL2 := 2 80ENABLE_TRF_FOR_NS := 2 81ENABLE_FEAT_ECV := 2 82ENABLE_FEAT_FGT := 2 83ENABLE_FEAT_FGT2 := 2 84ENABLE_FEAT_THE := 2 85ENABLE_FEAT_TCR2 := 2 86ENABLE_FEAT_S2PIE := 2 87ENABLE_FEAT_S1PIE := 2 88ENABLE_FEAT_S2POE := 2 89ENABLE_FEAT_S1POE := 2 90ENABLE_FEAT_SCTLR2 := 2 91ENABLE_FEAT_MTE2 := 2 92ENABLE_FEAT_LS64_ACCDATA := 2 93ENABLE_FEAT_AIE := 2 94ENABLE_FEAT_PFAR := 2 95ENABLE_FEAT_EBEP := 2 96 97ifeq (${ENABLE_RME},1) 98 ENABLE_FEAT_MEC := 2 99 RMMD_ENABLE_IDE_KEY_PROG := 1 100endif 101 102# The FVP platform depends on this macro to build with correct GIC driver. 103$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 104 105# Pass FVP_CLUSTER_COUNT to the build system. 106$(eval $(call add_define,FVP_CLUSTER_COUNT)) 107 108# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 109$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 110 111# Pass FVP_MAX_PE_PER_CPU to the build system. 112$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 113 114# Pass FVP_GICR_REGION_PROTECTION to the build system. 115$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 116 117# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 118$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 119 120# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 121# choose the CCI driver , else the CCN driver 122ifeq ($(FVP_CLUSTER_COUNT), 0) 123$(error "Incorrect cluster count specified for FVP port") 124else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 125FVP_INTERCONNECT_DRIVER := FVP_CCI 126else 127FVP_INTERCONNECT_DRIVER := FVP_CCN 128endif 129 130$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 131 132# Choose the GIC sources depending upon the how the FVP will be invoked 133ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 134USE_GIC_DRIVER := 3 135 136# The GIC model (GIC-600 or GIC-500) will be detected at runtime 137GICV3_SUPPORT_GIC600 := 1 138GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 139 140FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 141ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 142BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 143endif 144 145ifeq (${HW_ASSISTED_COHERENCY}, 0) 146FVP_DT_PREFIX := fvp-base-gicv3-psci 147else 148FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 149endif 150else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 151USE_GIC_DRIVER := 5 152ENABLE_FEAT_GCIE := 1 153BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 154FVP_DT_PREFIX := fvp-base-gicv5-psci 155ifneq ($(SPD),none) 156 $(error Error: GICv5 is not compatible with SPDs) 157endif 158ifeq ($(ENABLE_RME),1) 159 $(error Error: GICv5 is not compatible with RME) 160endif 161else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 162USE_GIC_DRIVER := 2 163 164# No GICv4 extension 165GIC_ENABLE_V4_EXTN := 0 166$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 167 168FVP_DT_PREFIX := fvp-base-gicv2-psci 169else 170$(error "Incorrect GIC driver chosen on FVP port") 171endif 172 173ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 174FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 175else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 176FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 177 plat/arm/common/arm_ccn.c 178else 179$(error "Incorrect CCN driver chosen on FVP port") 180endif 181 182FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 183 plat/arm/board/fvp/fvp_security.c \ 184 plat/arm/common/arm_tzc400.c 185 186 187PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 188 -Iinclude/lib/psa 189 190 191PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 192 193FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 194 195ifeq (${ARCH}, aarch64) 196 197# select a different set of CPU files, depending on whether we compile for 198# hardware assisted coherency cores or not 199ifeq (${HW_ASSISTED_COHERENCY}, 0) 200# Cores used without DSU 201 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 202 lib/cpus/aarch64/cortex_a53.S \ 203 lib/cpus/aarch64/cortex_a57.S \ 204 lib/cpus/aarch64/cortex_a72.S \ 205 lib/cpus/aarch64/cortex_a73.S 206else 207# Cores used with DSU only 208 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 209 # AArch64-only cores 210 # TODO: add all cores to the appropriate lists 211 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 212 lib/cpus/aarch64/cortex_a65ae.S \ 213 lib/cpus/aarch64/cortex_a76.S \ 214 lib/cpus/aarch64/cortex_a76ae.S \ 215 lib/cpus/aarch64/cortex_a77.S \ 216 lib/cpus/aarch64/cortex_a78.S \ 217 lib/cpus/aarch64/cortex_a78_ae.S \ 218 lib/cpus/aarch64/cortex_a78c.S \ 219 lib/cpus/aarch64/cortex_a710.S \ 220 lib/cpus/aarch64/cortex_a715.S \ 221 lib/cpus/aarch64/cortex_a720.S \ 222 lib/cpus/aarch64/cortex_a720_ae.S \ 223 lib/cpus/aarch64/neoverse_n1.S \ 224 lib/cpus/aarch64/neoverse_n2.S \ 225 lib/cpus/aarch64/neoverse_v1.S \ 226 lib/cpus/aarch64/neoverse_e1.S \ 227 lib/cpus/aarch64/cortex_x2.S \ 228 lib/cpus/aarch64/cortex_x4.S 229 endif 230 # AArch64/AArch32 cores 231 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 232 lib/cpus/aarch64/cortex_a75.S 233endif 234 235#Include all CPUs to build to support all-errata build. 236ifeq (${ENABLE_ERRATA_ALL},1) 237 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 238 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 239 lib/cpus/aarch64/cortex_a510.S \ 240 lib/cpus/aarch64/cortex_a520.S \ 241 lib/cpus/aarch64/cortex_a725.S \ 242 lib/cpus/aarch64/cortex_x1.S \ 243 lib/cpus/aarch64/cortex_x3.S \ 244 lib/cpus/aarch64/cortex_x925.S \ 245 lib/cpus/aarch64/neoverse_n3.S \ 246 lib/cpus/aarch64/neoverse_v2.S \ 247 lib/cpus/aarch64/neoverse_v3.S 248endif 249 250#Build AArch64-only CPUs with no FVP model yet. 251ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 252 ERRATA_SME_POWER_DOWN := 1 253 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 254 lib/cpus/aarch64/c1_nano.S \ 255 lib/cpus/aarch64/c1_ultra.S \ 256 lib/cpus/aarch64/c1_premium.S \ 257 lib/cpus/aarch64/canyon.S \ 258 lib/cpus/aarch64/caddo.S \ 259 lib/cpus/aarch64/veymont.S \ 260 lib/cpus/aarch64/dionysus.S \ 261 lib/cpus/aarch64/venom.S \ 262 lib/cpus/aarch64/lsc25_p_core.S \ 263 lib/cpus/aarch64/lsc25_e_core.S 264endif 265 266else 267FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 268 lib/cpus/aarch32/cortex_a57.S \ 269 lib/cpus/aarch32/cortex_a53.S 270endif 271 272BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 273 drivers/arm/sp805/sp805.c \ 274 drivers/delay_timer/delay_timer.c \ 275 drivers/io/io_semihosting.c \ 276 lib/semihosting/semihosting.c \ 277 lib/semihosting/${ARCH}/semihosting_call.S \ 278 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 279 plat/arm/board/fvp/fvp_bl1_setup.c \ 280 plat/arm/board/fvp/fvp_cpu_pwr.c \ 281 plat/arm/board/fvp/fvp_err.c \ 282 plat/arm/board/fvp/fvp_io_storage.c \ 283 plat/arm/board/fvp/fvp_topology.c \ 284 ${FVP_CPU_LIBS} \ 285 ${FVP_INTERCONNECT_SOURCES} 286 287ifeq (${USE_SP804_TIMER},1) 288BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 289else 290BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 291endif 292 293 294BL2_SOURCES += drivers/arm/sp805/sp805.c \ 295 drivers/io/io_semihosting.c \ 296 lib/utils/mem_region.c \ 297 lib/semihosting/semihosting.c \ 298 lib/semihosting/${ARCH}/semihosting_call.S \ 299 plat/arm/board/fvp/fvp_bl2_setup.c \ 300 plat/arm/board/fvp/fvp_err.c \ 301 plat/arm/board/fvp/fvp_io_storage.c \ 302 plat/arm/common/arm_nor_psci_mem_protect.c \ 303 ${FVP_SECURITY_SOURCES} 304 305 306ifeq (${COT_DESC_IN_DTB},1) 307BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 308endif 309 310ifeq (${ENABLE_RME},1) 311BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 312 plat/arm/board/fvp/fvp_cpu_pwr.c 313 314BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 315 plat/arm/board/fvp/fvp_realm_attest_key.c \ 316 plat/arm/board/fvp/fvp_el3_token_sign.c \ 317 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 318 plat/arm/common/plat_rmm_mem_carveout.c 319endif 320 321ifneq (${ENABLE_FEAT_RNG_TRAP},0) 322BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 323endif 324 325ifeq (${RESET_TO_BL2},1) 326BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 327 plat/arm/board/fvp/fvp_cpu_pwr.c \ 328 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 329 ${FVP_CPU_LIBS} \ 330 ${FVP_INTERCONNECT_SOURCES} 331endif 332 333ifeq (${USE_SP804_TIMER},1) 334BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 335endif 336 337BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 338 ${FVP_SECURITY_SOURCES} 339 340ifeq (${USE_SP804_TIMER},1) 341BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 342endif 343 344BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 345 drivers/arm/smmu/smmu_v3.c \ 346 drivers/delay_timer/delay_timer.c \ 347 drivers/cfi/v2m/v2m_flash.c \ 348 lib/utils/mem_region.c \ 349 plat/arm/board/fvp/fvp_bl31_setup.c \ 350 plat/arm/board/fvp/fvp_console.c \ 351 plat/arm/board/fvp/fvp_pm.c \ 352 plat/arm/board/fvp/fvp_topology.c \ 353 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 354 plat/arm/board/fvp/fvp_cpu_pwr.c \ 355 plat/arm/common/arm_nor_psci_mem_protect.c \ 356 ${FVP_CPU_LIBS} \ 357 ${FVP_INTERCONNECT_SOURCES} \ 358 ${FVP_SECURITY_SOURCES} 359 360# Support for fconf in BL31 361# Added separately from the above list for better readability 362ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 363BL31_SOURCES += lib/fconf/fconf.c \ 364 lib/fconf/fconf_dyn_cfg_getter.c \ 365 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 366 367BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 368 369ifeq (${SEC_INT_DESC_IN_FCONF},1) 370BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 371endif 372 373endif 374 375ifeq (${USE_SP804_TIMER},1) 376BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 377else 378BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 379endif 380 381# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 382FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 383 384FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 385$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 386HW_CONFIG := ${FVP_HW_CONFIG} 387 388HW_CONFIG_BASE ?= 0x82000000 389 390# Set default initrd base 128MiB offset of the default kernel address in FVP 391INITRD_BASE ?= 0x90000000 392 393# Kernel base address supports Linux kernels before v5.7 394# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 395ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 396 PRELOADED_BL33_BASE ?= 0x80080000 397 ifeq (${RESET_TO_BL31},1) 398 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 399 endif 400endif 401 402ifeq (${TRANSFER_LIST}, 0) 403FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 404 ${PLAT}_fw_config.dts \ 405 ${PLAT}_tb_fw_config.dts \ 406 ${PLAT}_soc_fw_config.dts \ 407 ${PLAT}_nt_fw_config.dts \ 408 ) 409 410FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 411FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 412FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 413FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 414 415ifeq (${SPD},tspd) 416FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 417FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 418 419# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 420$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 421endif 422 423# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 424$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 425# Add the NT_FW_CONFIG to FIP and specify the same to certtool 426$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 427endif 428 429ifeq (${SPD},spmd) 430 431ifeq ($(ARM_SPMC_MANIFEST_DTS),) 432ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 433endif 434 435FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 436FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 437 438# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 439$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 440endif 441 442# Add the HW_CONFIG to FIP and specify the same to certtool 443$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 444 445ifeq (${TRANSFER_LIST}, 1) 446 447ifeq ($(RESET_TO_BL31), 1) 448FW_HANDOFF_SIZE := 20000 449 450TRANSFER_LIST_DTB_OFFSET := 0x20 451$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 452endif 453endif 454 455ifeq (${HOB_LIST}, 1) 456include lib/hob/hob.mk 457endif 458 459# Enable dynamic mitigation support by default 460DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 461 462ifneq (${ENABLE_FEAT_AMU},0) 463BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 464 lib/cpus/aarch64/cpuamu_helpers.S 465 466ifeq (${HW_ASSISTED_COHERENCY}, 1) 467BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 468 lib/cpus/aarch64/neoverse_n1_pubsub.c 469endif 470endif 471 472ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 473 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 474 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 475 endif 476 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 477 plat/arm/board/fvp/aarch64/fvp_ea.c 478endif 479 480ifneq (${ENABLE_STACK_PROTECTOR},0) 481PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 482endif 483 484# Enable the dynamic translation tables library. 485ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 486 ifeq (${ARCH},aarch32) 487 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 488 else # AArch64 489 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 490 endif 491endif 492 493ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 494 ifeq (${ARCH},aarch32) 495 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 496 else # AArch64 497 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 498 ifeq (${SPD},tspd) 499 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 500 endif 501 endif 502endif 503 504ifeq (${USE_DEBUGFS},1) 505 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 506endif 507 508# Add support for platform supplied linker script for BL31 build 509PLAT_EXTRA_LD_SCRIPT := 1 510 511ifneq (${RESET_TO_BL2}, 0) 512 override BL1_SOURCES = 513endif 514 515include plat/arm/board/common/board_common.mk 516include plat/arm/common/arm_common.mk 517 518ifeq (${MEASURED_BOOT},1) 519BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 520 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 521 lib/psa/measured_boot.c 522 523BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 524 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 525 lib/psa/measured_boot.c 526endif 527 528ifeq (${DRTM_SUPPORT}, 1) 529BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 530 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 531 plat/arm/board/fvp/fvp_drtm_err.c \ 532 plat/arm/board/fvp/fvp_drtm_measurement.c \ 533 plat/arm/board/fvp/fvp_drtm_stub.c \ 534 plat/arm/common/arm_dyn_cfg.c \ 535 plat/arm/board/fvp/fvp_err.c 536endif 537 538ifeq (${TRUSTED_BOARD_BOOT}, 1) 539BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 540BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 541 542# FVP being a development platform, enable capability to disable Authentication 543# dynamically if TRUSTED_BOARD_BOOT is set. 544DYN_DISABLE_AUTH := 1 545endif 546 547ifeq (${SPMC_AT_EL3}, 1) 548PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 549endif 550 551PSCI_OS_INIT_MODE := 1 552 553ifeq (${SPD},spmd) 554BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 555endif 556 557# Test specific macros, keep them at bottom of this file 558$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 559ifeq (${PLATFORM_TEST_EA_FFH}, 1) 560 ifeq (${FFH_SUPPORT}, 0) 561 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 562 endif 563 564endif 565 566PLATFORM_TEST_RAS_FFH ?= 0 567$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 568ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 569 ifeq (${ENABLE_FEAT_RAS}, 0) 570 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 571 endif 572 ifeq (${SDEI_SUPPORT}, 0) 573 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 574 endif 575 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 576 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 577 endif 578endif 579 580$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 581ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 582 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 583 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 584 endif 585 ifeq (${ENABLE_SPMD_LP}, 0) 586 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 587 endif 588 ifeq (${ENABLE_FEAT_RAS}, 0) 589 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 590 endif 591 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 592 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 593 endif 594endif 595 596ifeq (${ERRATA_ABI_SUPPORT}, 1) 597include plat/arm/board/fvp/fvp_cpu_errata.mk 598endif 599 600# Build macro necessary for running SPM tests on FVP platform 601$(eval $(call add_define,PLAT_TEST_SPM)) 602 603ifeq (${LFA_SUPPORT},1) 604BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 605endif 606 607# This is set to 1 by default when the firmware update 608# support is enabled. Since the BL2 image is not updatable 609ifeq ($(PSA_FWU_SUPPORT),1) 610 SEPARATE_BL2_FIP := 1 611endif 612 613ifeq (${TRANSFER_LIST}, 0) 614ifeq (${SEPARATE_BL2_FIP},1) 615$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 616$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 617else 618$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 619$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 620endif 621endif 622