fix(fvp): increase resident text size of BL2

Enabling new CPU library code like Venom requires to set build flags
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0. When build along with
RESET_TO_BL=1 (BL2

fix(fvp): increase resident text size of BL2

Enabling new CPU library code like Venom requires to set build flags
HW_ASSISTED_COHERENCY=1 USE_COHERENT_MEM=0. When build along with
RESET_TO_BL=1 (BL2 in EL3 case) causes increase in resident text size
of BL2.

This is applicable in case of PLAT=fvp as it includes a lot of CPU_LIBS
and might not be the case of other platforms as it includes only
specific CPU libs.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I2fd7eecebd9a2bdcbdc9fbbf4cecc2d659740931

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refactor(fvp): use SZ_* defs fr event log

Switch `PLAT_ARM_EVENT_LOG_MAX_SIZE` to SZ_* helpers for readability.

Change-Id: I9375fad3232afb9c3dc58204cc915d9c7fb2957f
Signed-off-by: Harrison Mutai <h

refactor(fvp): use SZ_* defs fr event log

Switch `PLAT_ARM_EVENT_LOG_MAX_SIZE` to SZ_* helpers for readability.

Change-Id: I9375fad3232afb9c3dc58204cc915d9c7fb2957f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(rme): increase worst-case event size

Increase the worst-case event log size for RME. It's now possible for
each event to hold up to `LIBEVLOG_MAX_HASH_COUNT` digests. Increase the
worst-case siz

fix(rme): increase worst-case event size

Increase the worst-case event log size for RME. It's now possible for
each event to hold up to `LIBEVLOG_MAX_HASH_COUNT` digests. Increase the
worst-case size to account for this.

Change-Id: Ie072f9fe1ea5617c030556fae4c8c893cfefc4e0
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(fvp): use crypto-agile measured boot

Update the FVP measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection

refactor(fvp): use crypto-agile measured boot

Update the FVP measured boot flow to use the crypto-agile API. Replace
the previous single-algorithm hash configuration with dynamic algorithm
selection. Align image measurement and event log header generation with
the new hashing model and update platform glue code accordingly.

Change-Id: I4128a0c66a56df6c473c47a577d86cd38bf057f6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "feat(fvp): load SP_PKGs with TRANSFER_LIST" into integration

feat(fvp): extend image decryption support for FVP

Add encryption IO layer to be stacked above FIP IO layer for optional
encryption of the BL31 and BL32 images in case the ENCRYPT_BL31 or
ENCRYPT_BL

feat(fvp): extend image decryption support for FVP

Add encryption IO layer to be stacked above FIP IO layer for optional
encryption of the BL31 and BL32 images in case the ENCRYPT_BL31 or
ENCRYPT_BL32 build flag is set.

Enable decryption support for FVP through setting the DECRYPTION_SUPPORT
build flag. "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated
decryption using AES-GCM algorithm.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Iebc3b360b4a0dc0d933b816d28015ac551b79405

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feat(fvp): load SP_PKGs with TRANSFER_LIST

To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_trans

feat(fvp): load SP_PKGs with TRANSFER_LIST

To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_transfer_list_dyn_cfg_init().

Since there is no standard tag_id defined for TB_FW_CONFIG in the
transfer list, define PLAT_ARM_TB_FW_CONFIG_TL_TAG as a platform-specific
identifier to load TB_FW_CONFIG.

With this change, BL2 can load the SP_PKGs specified in TB_FW_CONFIG.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I2470c1ef3bf2bf921d0de1fff541565df13eaee4

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fix(fvp): use global option for setting PLAT_ARM_MAX_BL2_SIZE

Use global option TRUSTED_BOARD_BOOT for setting PLAT_ARM_MAX_BL2_SIZE.

Change-Id: Ia360b36535d2039de8e41da90dd4c8478adb6d54
Signed-off

fix(fvp): use global option for setting PLAT_ARM_MAX_BL2_SIZE

Use global option TRUSTED_BOARD_BOOT for setting PLAT_ARM_MAX_BL2_SIZE.

Change-Id: Ia360b36535d2039de8e41da90dd4c8478adb6d54
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(arm): derive RMM bank size from payload

Compute the RMM bank size as half of the RMM payload size instead of
using a hardcoded value. This removes duplication and keeps the bank
size automatical

fix(arm): derive RMM bank size from payload

Compute the RMM bank size as half of the RMM payload size instead of
using a hardcoded value. This removes duplication and keeps the bank
size automatically in sync with payload size changes.

Change-Id: I064390ec50115929bf6248344bf08a19fbc15344
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(arm): move lfa componet header to common and fix the helper

Move the FVP LFA component definitions to include/plat/arm/common/
so they can be shared by all Arm platforms, and update include
path

fix(arm): move lfa componet header to common and fix the helper

Move the FVP LFA component definitions to include/plat/arm/common/
so they can be shared by all Arm platforms, and update include
paths accordingly.

On FVP, rename the input parameter to lfa_component_id to match
the function declaration, and fix callers to pass the component
ID (not image_id) to the prime-complete helper.

Change-Id: Ia1485096819d6523c4bee14c602cbde3c6e144ef
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(gpt): fix fill_l1_cont_desc() function" into integration

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition table at
runtime, so a fixed offset is unnecessary. Also cleaned up the FIP
address handling comment for clarity.

Change-Id: I03f003a9307d66d16666eefcff1f45bb010779c9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SP

Merge changes from topic "rustspmc_with_xferlist" into integration

* changes:
feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm
feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry
feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
feat(spmd): get spmc manifest from xferlist

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feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition

PLAT_ARM_SPMC_SP_MANIFEST_SIZE is used to allocate transfer entry
when TF-A is built with TRANSFER_LIST to pass:
- StandaloneMm manifest w

feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition

PLAT_ARM_SPMC_SP_MANIFEST_SIZE is used to allocate transfer entry
when TF-A is built with TRANSFER_LIST to pass:
- StandaloneMm manifest with TL_TAG_DT_FFA_MANIFEST tag
in case of SPMC_AT_EL3

- SPMC manifest (i.e) rust-spmc.

Therefore, move the PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition
under the TRNASFER_LIST & SPD_spmd condition and increase
the size of TRANSFER_LIST as much as PLAT_ARM_SPMC_SP_MANIFEST_SIZE

Change-Id: If5e4c184fcf3aa683554f6d49caf78a5f6bfc2d1
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single

fix(gpt): fix fill_l1_cont_desc() function

GPT library function fill_l1_cont_desc() writes
contiguous descriptors and is called in a loop
by fill_l1_tbl() which fills out GPI entries in
in a single L1 table. The loop terminates when
the address of the first granule in range 'first'
exceeds address of the last granule (inclusive)
'last'.
This patch fixes the issue when fill_l1_cont_desc()
was iterating through all matching contiguous block
sizes 512, 32 and 2MB in a loop and filling consecutive
smaller descriptors instead of filling a single one with
a maximum size. This resulted for memory region 0x80000000
of size 1.5GB (3*512MB)to be filled with 2 512MB, 8 32MB and
128 2MB contiguous descriptors instead of 3 512MB descriptors
with build option RME_GPT_MAX_BLOCK=512.
This patch also removes unused definition of ARM_PAS_GPI_ANY
macro in fvp_pas_def.h.

Change-Id: I9fcff512af306a57d17dee0bade74d2f3f79b5e9
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(fvp): increase PLAT_ARM_SPMC_SIZE for rust-spmc

rust-spmc [0] which is experimental S-EL1 SPMC uses
PLAT_ARM_TRUSTED_DRAM area to run itself as much as
16MB (half of PLAT_ARM_TRUSTED_DRAM).

Ho

feat(fvp): increase PLAT_ARM_SPMC_SIZE for rust-spmc

rust-spmc [0] which is experimental S-EL1 SPMC uses
PLAT_ARM_TRUSTED_DRAM area to run itself as much as
16MB (half of PLAT_ARM_TRUSTED_DRAM).

However since PLAT_ARM_SPMC_SIZE is defined as 2MB,
the memory layout specified in arm_spm_def.h defines wrong value.
(i.e) PLAT_SPM_BUF_BASE, secure crb buffer and etc.

To resolve this increase the PLAT_ARM_SPMC_SIZE to 16MB.

Link: https://git.trustedfirmware.org/rust-spmc/rust-spmc.git [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ief207d787dd83e7a8e3c55f39fbc25d964ee8b25

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feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMA

feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: I4c3cbf6242f2ccf154b93e9497ab9a21a4b67772
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIF

feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIFEST_SIZE with PAGE_SIZE taken
from PLAT_ARM_HW_CONFIG_SIZE by reducing it as amount of
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

2. increase HAND_OFF transfer list size as much as
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

Change-Id: I56be7783ee4d257e33148f1f623a64bc498f1955
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off

feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length

feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length by this much to allow to
build these two configurations together.

Change-Id: Ifaeee5010143b53ba4f43c45011eaa8a28456bc5
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLA

feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: If48e2eb90e3d4319b0588e4467f2bda0fbaf9a64
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Lin

feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ic784dfcce921182968854a0fc90487754a8f59c8

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feat(fvp): implement LFA get components API

Introduce platform-specific implementation of
`plat_lfa_get_components()` for the Arm FVP platform. This function
returns LFA component metadata, includin

feat(fvp): implement LFA get components API

Introduce platform-specific implementation of
`plat_lfa_get_components()` for the Arm FVP platform. This function
returns LFA component metadata, including component ID, UUID for
each supported firmware image and number of components.

Change-Id: I9e7cbce5865becf3e4babcb770bc5eb3b69a0be8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "chore(fvp): remove unused macro definition" into integration