1/* 2 * Copyright (c) 2022-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v3.h> 11#include "wa_cve_2022_23960_bhb_vector.S" 12 13#include <cpu_macros.S> 14#include <wa_cve_2025_0647_cpprctx.h> 15 16#include <plat_macros.S> 17 18/* Hardware handled coherency */ 19#if HW_ASSISTED_COHERENCY == 0 20#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 21#endif 22 23/* 64-bit only core */ 24#if CTX_INCLUDE_AARCH32_REGS == 1 25#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 26#endif 27 28cpu_reset_prologue neoverse_v3 29 30.global check_erratum_neoverse_v3_3701767 31 32workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647 33 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 34 ldr x0, =0x1 35 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 36 ldr x0, =0xd5380000 37 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 38 ldr x0, =0xFFFFFF40 39 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 40 ldr x0, =0x000080010033f 41 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 42 isb 43workaround_reset_end neoverse_v3, ERRATUM(2970647) 44 45check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0) 46 47workaround_runtime_start neoverse_v3, ERRATUM(3312417), ERRATA_V3_3312417 48 speculation_barrier 49workaround_runtime_end neoverse_v3, ERRATUM(3312417) 50 51check_erratum_ls neoverse_v3, ERRATUM(3312417), CPU_REV(0, 1) 52 53workaround_reset_start neoverse_v3, ERRATUM(3696307), ERRATA_V3_3696307 54 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 55workaround_reset_end neoverse_v3, ERRATUM(3696307) 56 57check_erratum_ls neoverse_v3, ERRATUM(3696307), CPU_REV(0, 1) 58 59add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767 60 61check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2) 62 63workaround_reset_start neoverse_v3, ERRATUM(3734562), ERRATA_V3_3734562 64 mov x0, #2 65 msr NEOVERSE_V3_CPUPSELR_EL3, x0 66 ldr x0, =0xD503225F 67 msr NEOVERSE_V3_CPUPOR_EL3, x0 68 mov x0, 0xFFFFFFFF 69 msr NEOVERSE_V3_CPUPMR_EL3, x0 70 ldr x0, =0x404003FD 71 msr NEOVERSE_V3_CPUPCR_EL3, x0 72workaround_reset_end neoverse_v3, ERRATUM(3734562) 73 74check_erratum_ls neoverse_v3, ERRATUM(3734562), CPU_REV(0, 1) 75 76workaround_reset_start neoverse_v3, ERRATUM(3782181), ERRATA_V3_3782181 77 /* Disable retention control for WFI and WFE. */ 78 mrs x0, NEOVERSE_V3_CPUPWRCTLR_EL1 79 bfi x0, xzr, #NEOVERSE_V3_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 80 #NEOVERSE_V3_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 81 bfi x0, xzr, #NEOVERSE_V3_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 82 #NEOVERSE_V3_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 83 msr NEOVERSE_V3_CPUPWRCTLR_EL1, x0 84workaround_reset_end neoverse_v3, ERRATUM(3782181) 85 86check_erratum_range neoverse_v3, ERRATUM(3782181), CPU_REV(0, 1), \ 87 CPU_REV(0, 1) 88 89workaround_reset_start neoverse_v3, ERRATUM(3864536), ERRATA_V3_3864536 90 sysreg_bit_set NEOVERSE_V3_CPUACTLR2_EL1, BIT(22) 91workaround_reset_end neoverse_v3, ERRATUM(3864536) 92 93check_erratum_ls neoverse_v3, ERRATUM(3864536), CPU_REV(0, 2) 94 95workaround_reset_start neoverse_v3, ERRATUM(3878291), ERRATA_V3_3878291 96 sysreg_bit_set NEOVERSE_V3_CPUACTLR4_EL1, BIT(57) 97workaround_reset_end neoverse_v3, ERRATUM(3878291) 98 99check_erratum_ls neoverse_v3, ERRATUM(3878291), CPU_REV(0, 2) 100 101/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 102workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 103 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 104workaround_reset_end neoverse_v3, CVE(2024, 5660) 105 106check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 107 108 /* ---------------------------------------------------------------- 109 * CVE-2024-7881 is mitigated for Neoverse-V3 / Neoverse-V3AE 110 * using erratum 3696307 workaround by disabling the 111 * affected prefetcher setting CPUACTLR6_EL1[41]. 112 * ---------------------------------------------------------------- 113 */ 114workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 115 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 116workaround_reset_end neoverse_v3, CVE(2024, 7881) 117 118check_erratum_ls neoverse_v3, CVE(2024, 7881), CPU_REV(0, 1) 119 120 /* 121 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 122 * Enables mitigation for CVE-2025-0647. 123 */ 124workaround_reset_start neoverse_v3, CVE(2025, 647), WORKAROUND_CVE_2025_0647 125 mov x0, #WA_PATCH_SLOT(3) 126 bl wa_cve_2025_0647_instruction_patch 127workaround_reset_end neoverse_v3, CVE(2025, 647) 128 129check_erratum_chosen neoverse_v3, CVE(2025, 647), WORKAROUND_CVE_2025_0647 130 131#if WORKAROUND_CVE_2025_0647 132func neoverse_v3_impl_defined_el3_handler 133 mov x0, #0 134 135 /* See if this call came from trap handler. */ 136 cmp x1, #EC_IMP_DEF_EL3 137 bne wa_cve_2025_0647_do_cpp_wa 138 orr x0, x0, #WA_IS_TRAP_HANDLER 139 b wa_cve_2025_0647_do_cpp_wa 140endfunc neoverse_v3_impl_defined_el3_handler 141#endif 142 143 /* --------------------------------------------- 144 * HW will do the cache maintenance while powering down 145 * --------------------------------------------- 146 */ 147func neoverse_v3_core_pwr_dwn 148 /* --------------------------------------------- 149 * Enable CPU power down bit in power control register 150 * --------------------------------------------- 151 */ 152 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 153 NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 154 155 isb 156 ret 157endfunc neoverse_v3_core_pwr_dwn 158 159cpu_reset_func_start neoverse_v3 160 /* Disable speculative loads */ 161 msr SSBS, xzr 162 apply_erratum neoverse_v3, ERRATUM(3312417), ERRATA_V3_3312417 163cpu_reset_func_end neoverse_v3 164 165 /* --------------------------------------------- 166 * This function provides Neoverse V3 specific 167 * register information for crash reporting. 168 * It needs to return with x6 pointing to 169 * a list of register names in ascii and 170 * x8 - x15 having values of registers to be 171 * reported. 172 * --------------------------------------------- 173 */ 174.section .rodata.neoverse_v3_regs, "aS" 175neoverse_v3_regs: /* The ascii list of register names to be reported */ 176 .asciz "cpuectlr_el1", "" 177 178func neoverse_v3_cpu_reg_dump 179 adr x6, neoverse_v3_regs 180 mrs x8, NEOVERSE_V3_CPUECTLR_EL1 181 ret 182endfunc neoverse_v3_cpu_reg_dump 183 184#if WORKAROUND_CVE_2025_0647 185declare_cpu_ops_eh neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 186 neoverse_v3_reset_func, \ 187 neoverse_v3_impl_defined_el3_handler, \ 188 neoverse_v3_core_pwr_dwn 189 190declare_cpu_ops_eh neoverse_v3, NEOVERSE_V3_MIDR, \ 191 neoverse_v3_reset_func, \ 192 neoverse_v3_impl_defined_el3_handler, \ 193 neoverse_v3_core_pwr_dwn 194#else 195declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 196 neoverse_v3_reset_func, \ 197 neoverse_v3_core_pwr_dwn 198 199declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \ 200 neoverse_v3_reset_func, \ 201 neoverse_v3_core_pwr_dwn 202#endif 203