fix(corstone-1000): use generic hold pen

Convert corstone1000 to use the common hold pen helpers, fixing a
cache coherency bug in secondary CPU bring-up.

The original code used 8-byte hold slots (n

fix(corstone-1000): use generic hold pen

Convert corstone1000 to use the common hold pen helpers, fixing a
cache coherency bug in secondary CPU bring-up.

The original code used 8-byte hold slots (not cache-line aligned)
and only wrote GO to the target slot without touching other slots
or flushing to main memory. This is broken because:

1. Secondary CPUs write WAIT from non-cached context (MMU off in BL2)
2. The BL2-to-BL31 transition does dcsw_op_all (flush all caches)
3. This pushes stale cached data over the WAIT values in memory
4. The primary's GO write + DSB is insufficient -- it only ensures
ordering, not visibility to non-cached observers

plat_hold_pen_init() is called once at boot (from
plat_arm_psci_override_pm_ops) to write HOLD_STATE_WAIT into every
cache-line-aligned slot and flush the region. Then
plat_hold_pen_signal() writes just the target slot with the warm
boot entrypoint, flushes it, and issues SEV. Secondaries use the
plat_hold_pen_wait_and_jump macro to poll and branch directly to
the entrypoint stored in their hold slot.

Change-Id: I8fc533650c663700dab9bf47c0a79d9bb1236b17
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

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Merge changes I361f587a,Idc704ece,I5529dbe5 into integration

* changes:
fix(gic): init the GIC before the platform with a hook
refactor(arm): set the transfer list up earlier
refactor(el3-runt

Merge changes I361f587a,Idc704ece,I5529dbe5 into integration

* changes:
fix(gic): init the GIC before the platform with a hook
refactor(arm): set the transfer list up earlier
refactor(el3-runtime): use arm_gicr_base_addrs for sp-min

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feat(corstone-1000): make mutlicore support platform generic

To improve portability, testing coverage, and future platform
enablement.

- Replace FVP-only multicore checks with platform-generic chec

feat(corstone-1000): make mutlicore support platform generic

To improve portability, testing coverage, and future platform
enablement.

- Replace FVP-only multicore checks with platform-generic checks.

Change-Id: Ib52bbd8ce1850bbc7d5f72e6f29a208c3ba534d3
Signed-off-by: Alex Chapman <alex.chapman@arm.com>

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fix(gic): init the GIC before the platform with a hook

While GIC setup is generic across platforms, its usage is not. Some
platforms won't use it at EL3, while others need to configure interrupts
(l

fix(gic): init the GIC before the platform with a hook

While GIC setup is generic across platforms, its usage is not. Some
platforms won't use it at EL3, while others need to configure interrupts
(like RAS) in the standard platform hooks. To do that, the GIC needs to
be set up and ready to use before calling the platform hooks but
currently that is only done after. Annoyingly, a handful of platforms
need to set their GIC up before initialising it necessitating the
platform hooks to be called before GIC init.

This patch resolves this contradiction by moving the general GIC setup
calls to before the platform hooks and adding a GIC-specific platform
hook just before GIC per CPU init. This way both types of platforms can
do their business at the same time.

Change-Id: I361f587ab4603162ee880addb074800cbbb97b49
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FE

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FEATURE. Setting -march directly can lead to unexpected results
when using the above flags and is generally not recommended within tfa.

This patch migrates all instances of -march=armv8-a+crc to
ARM_ARCH_FEATURE=crc. Arm platforms (via arm_common.mk) are checked and
those that support cores greater than arm8.1 do not get the flag as it
is automatically pulled in.

Change-Id: I846f97367eab9529524a2805d5b87d34cce2360f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(corstone-1000): add Cortex-A320 support

Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
Corstone-1000 while keeping Cortex-A35 as the default. When the
define is enabled, the buil

feat(corstone-1000): add Cortex-A320 support

Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
Corstone-1000 while keeping Cortex-A35 as the default. When the
define is enabled, the build switches from `cortex_a35.S` to
`cortex_a320.S`, maintaining compatibility with existing A35-based
designs.

Also add Normal-World mappings for the Ethos-U85 NPU and its SRAM
on Cortex-A320 platforms so U-Boot and other non-secure software
can safely access these regions:

* **Ethos-U85 registers**: base `0x1A050000`, size `0x00004000` (16 KB),
attrs `MT_DEVICE | MT_RW | MT_NS`
* **Non-secure SRAM**: base `0x02400000`, size `0x00400000` (4 MB),
attrs `MT_MEMORY | MT_RW | MT_NS`

Enable GICv3 with GIC-600 when building for Cortex-A320 (retain
GICv2/GIC-400 for Cortex-A35):

* Update `plat_my_core_pos()` and `plat_arm_calc_core_pos()` to use
the Cortex-A320 MPIDR_EL1 affinity layout.
* Add an A320-specific core-position routine in assembly guarded by
`CORSTONE1000_CORTEX_A320`.
* Switch to the GICv3 driver with GIC-600 extensions: update GIC base
addresses, use GICv3 APIs, and set `USE_GIC_DRIVER=3`,
`GICV3_SUPPORT_GIC600=1`, `GIC_ENABLE_V4_EXTN=1`.

These changes prepare the platform for Cortex-A320 integration and
ensure correct GIC configuration and secondary-core bring-up, while
preserving A35 behavior.

Change-Id: Ief03dd528e67918e160d5b42ad1344b0ba3440f8
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
Signed-off-by: Michael Safwat <michael.safwat@arm.com>

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feat(arm): allow custom BL2 mem params

Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this overri

feat(arm): allow custom BL2 mem params

Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this override is enabled,
the common arm_bl2_mem_params_desc.c implementation is
excluded from BL2_SOURCES. The platform must then append
its own bl2_mem_params_desc.c file to BL2_SOURCES.

Change-Id: I8e3e0ce6e9c2c55ec3feb18a45890f1716fe690b
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition table at
runtime, so a fixed offset is unnecessary. Also cleaned up the FIP
address handling comment for clarity.

Change-Id: I03f003a9307d66d16666eefcff1f45bb010779c9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos(

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos() no longer needs to be called
within the driver, helping with performance a bit.

Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is

refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is difficult as their use is platform specific. So copy them to a
generic place and redirect platforms to them.

The new copies will remain for compatibility for platforms that don't
want to or can't take up upcoming refactors and the old copies can be
drastically refactored to make them more widely applicable.

Change-Id: I056c8710cdda4d8a81b324d392762c29e02cdae1
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(arm): convert arm platforms to expect a wakeup

Newer cores in upcoming platforms may refuse to power down. The PSCI
library is already prepared for this so convert platform code to also
allow t

feat(arm): convert arm platforms to expect a wakeup

Newer cores in upcoming platforms may refuse to power down. The PSCI
library is already prepared for this so convert platform code to also
allow this. This is simple - drop the `wfi` + panic and let common code
deal with the fallout. The end result will be the same (sans the
message) except the platform will have fewer responsibilities. The only
exception is for cores being signalled to power off gracefully ahead of
system reset. That path must also be terminal so replace the end with
the same psci_pwrdown_cpu_end() to behave the same as the generic
implementation. It will handle wakeups and panic, hoping that the system
gets reset from under it. The dmb is upgraded to a dsb so no functional
change.

Change-Id: I381f96bec8532bda6ccdac65de57971aac42e7e8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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