refactor(cpus): modify log for "ERRATA_NOT_APPLIES"

modify the print logs when an erratum workaround does not
need to be applied to a certain revision/variant of the CPU.

Change-Id: I8f60636320f617

refactor(cpus): modify log for "ERRATA_NOT_APPLIES"

modify the print logs when an erratum workaround does not
need to be applied to a certain revision/variant of the CPU.

Change-Id: I8f60636320f617ecd4ed88ee1fbf7a3e3e4517ee
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(fgt2): add support for FEAT_FGT2

This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash

feat(fgt2): add support for FEAT_FGT2

This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a

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feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed

feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a

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chore(cm): fix some typos in comments

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I592439f1686c333c855de98a8e7d377ba1e6c498

Merge "feat(cm): context switch MDCR_EL3 register" into integration

Merge "refactor(cm): update SCTLR_EL2 initialisation" into integration

feat(cm): context switch MDCR_EL3 register

Currently MDCR_EL3 register value is same for all the
worlds(Non-secure, Secure, Realm and Root).

With this approach, features enable/disable settings
rem

feat(cm): context switch MDCR_EL3 register

Currently MDCR_EL3 register value is same for all the
worlds(Non-secure, Secure, Realm and Root).

With this approach, features enable/disable settings
remain same across all the worlds. This is not ideal as
there must be flexibility in controlling feature as per
the requirements for individual world.

The patch addresses this by providing MDCR_EL3 a per world
value. Features with identical values for all the worlds are
grouped under ``manage_extensions_common`` API.

Change-Id: Ibc068d985fe165d8cb6d0ffb84119bffd743b3d1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(gpt): fix GPT library fill_l1_tbl() function

GPT library function fill_l1_tbl() gets 'first' and
'last' parameters which are the start addresses of
the 1st and the last granules in the range to

fix(gpt): fix GPT library fill_l1_tbl() function

GPT library function fill_l1_tbl() gets 'first' and
'last' parameters which are the start addresses of
the 1st and the last granules in the range to fill
L1 GPT table. When RME_GPT_MAX_BLOCK build option
is not 0, condition for 'while' loop should be
changed from 'first < last' to 'first <= last' in
the case of 'first' = 'last' when a single granule
is passed.

Change-Id: I9b49a78b5a2f7a01f51dbce43bd3f3cfbb458fa2
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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refactor(cm): update SCTLR_EL2 initialisation

Currently, during the initial bootup phase SCTLR_EL2 register
has been initialised with the endianness bit based on header
attribute evaluation at EL3.

refactor(cm): update SCTLR_EL2 initialisation

Currently, during the initial bootup phase SCTLR_EL2 register
has been initialised with the endianness bit based on header
attribute evaluation at EL3.

This is not mandatorily required as TF-A by default, expects
the software at EL2 to execute in little endian format ( EE = 0).

Henceforth, this patch removes the endianness bit evaluation for
SCTLR_EL2 register and initialises with a predefined RESET value,
setting SCTLR_EL2.EE=0.

Change-Id: I53fdd5bf907cbe35c551fc03cc893821229ff807
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables

build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).

These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:

make --silent V=1

... results in a silent build.

In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.

When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed but not echoed'

When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed and echoed'

In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:

$(s)echo 'This command is executed but not echoed'
$(q)echo 'This command is executed but not echoed'

The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.

Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch

Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch attestation key and token from RSE
feat(psa): introduce generic library for CCA attestation
feat(rdfremont): initialize the rse comms driver
feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3
fix(rse): include lib-psa to resolve build
feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms
feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms
feat(rdfremont): initialize GPT on GPC SMMU block
feat(rdfremont): update Root registers page offset for SMMUv3
feat(rdfremont): enable MTE2 if present on the platform
feat(rdfremont): enable SVE for SWD and NS
feat(rdfremont): enable AMU if present on the platform
feat(rdfremont): enable MPAM if present on the platform
feat(rdfremont): add DRAM pas entries in pas table for multichip
feat(rdfremont): add implementation for GPT setup
feat(rdfremont): integrate DTS files for RD-Fremont variants
feat(rdfremont): add support for RD-Fremont-Cfg2
feat(rdfremont): add support for RD-Fremont-Cfg1
feat(rdfremont): add support for RD-Fremont
feat(neoverse-rd): add scope for RD-Fremont variants
feat(neoverse-rd): add multichip pas entries
feat(neoverse-rd): add pas definitions for third gen platforms
feat(neoverse-rd): add DRAM layout for third gen platforms
feat(neoverse-rd): add SRAM layout for third gen platforms
feat(neoverse-rd): add firmware definitions for third gen platforms
feat(neoverse-rd): add RoS definitions for third gen platforms
feat(neoverse-rd): add CSS definitions for third gen platforms

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feat(psa): introduce generic library for CCA attestation

Add a generic Arm CCA attestation library driver to interface with the
PSA delegated attestation partition APIs that use RSE to fetch the
pla

feat(psa): introduce generic library for CCA attestation

Add a generic Arm CCA attestation library driver to interface with the
PSA delegated attestation partition APIs that use RSE to fetch the
platform attestation token and Realm attestation key.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I882273e97567cc068f90d2ef089410f3a93c6b00

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feat(rockchip): add RK3566/RK3568 Socs support

RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. su

feat(rockchip): add RK3566/RK3568 Socs support

RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c

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Merge "fix(gpt): fix RME GPT library bug" into integration

fix(gpt): fix RME GPT library bug

This patch fixes fill_l1_tbl() function bug
for RME_GPT_MAX_BLOCK build option set to 0
disabling filling L1 tables with Contiguous
descriptors.

Change-Id: I3eedd6

fix(gpt): fix RME GPT library bug

This patch fixes fill_l1_tbl() function bug
for RME_GPT_MAX_BLOCK build option set to 0
disabling filling L1 tables with Contiguous
descriptors.

Change-Id: I3eedd6c1bb55b7c207bb3630d1ab2fda8f72eb17
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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build(romlib): don't timestamp generated wrappers

The Makefile rule for the libwrappers object files places a dependency
on a timestamp file. This timestamp file is created by the recipe that
genera

build(romlib): don't timestamp generated wrappers

The Makefile rule for the libwrappers object files places a dependency
on a timestamp file. This timestamp file is created by the recipe that
generates the libwrappers sources, and was presumably introduced to
indicate to Make that all of the source files are generated
simultaneously by that rule.

Instead, we can use a grouped target rule, which uses `&:` instead of
`:`. This communicates to Make that all of the targets listed are
generated at once.

To demonstrate, the following two Makefile rules differ in their
behaviour:

a.x b.x c.x: # targets may be updated independently
... # generate a.x, b.x and c.x

a.x b.x c.x &: # all targets are updated at once
... # generate a.x, b.x and c.x

While both recipes do generate all three files, only the second rule
communicates this fact to Make. As such, Make can reason that if one of
the files is up to date then all of them are, and avoid re-running the
rule for any generated file that it has not already run it for.

Change-Id: I10b49eb72b5276c7f9bd933900833b03a61cff2f
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(romlib): de-duplicate ROMLib wrapper sources

The `romlib_generator.py` script may generate duplicate wrapper sources,
which is undesirable when using them to generate Makefile rules as Make
wi

build(romlib): de-duplicate ROMLib wrapper sources

The `romlib_generator.py` script may generate duplicate wrapper sources,
which is undesirable when using them to generate Makefile rules as Make
will warn about duplicated targets.

This change sorts the wrapper sources returned from this script, which
has the effect of also de-duplicating them.

Change-Id: I109607ef94f77113a48cc0d6e07877efd1971dbc
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "refactor(cm): move mpam registers into el2 context" into integration

chore: rename Blackhawk to Cortex-X925

Rename Blackhawk to Cortex-X925.

Change-Id: I51e40a7bc6b8871c53c40d1f341853b1fd7fdf71
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename Chaberton to Cortex-A725

Rename Chaberton to Cortex-A725.

Change-Id: I981b22d3b37f1aa6e25ff1f35aa156fff9c30076
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

refactor(cm): move mpam registers into el2 context

* FEAT_MPAM related EL2 registers are placed explicitly outside
the EL2 context in the cpu_context_t structure.

* With EL2 registers now coupled

refactor(cm): move mpam registers into el2 context

* FEAT_MPAM related EL2 registers are placed explicitly outside
the EL2 context in the cpu_context_t structure.

* With EL2 registers now coupled with dependent features, this
patch moves them to the el2_context structure "el2_sysregs_t".

* Further, converting the assembly context-offset entries into a
c structure. It relies on garbage collection of the linker
removing unreferenced structures from memory, as well as aiding
in readability and future maintenance.

Change-Id: Ib784bc8d2fbe35a8a47a569426d8663282ec06aa
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge changes I710d1780,Ia9a59bde into integration

* changes:
feat(gpt): configure memory size protected by bitlock
feat(gpt): add support for large GPT mappings

feat(gpt): configure memory size protected by bitlock

This patch adds support in GPT library for configuration
of the memory block size protected by one bit of 'bitlock'
structure. Build option 'RME

feat(gpt): configure memory size protected by bitlock

This patch adds support in GPT library for configuration
of the memory block size protected by one bit of 'bitlock'
structure. Build option 'RME_GPT_BITLOCK_BLOCK' defines the
number of 512MB blocks covered by each bit. This numeric
parameter must be a power of 2 and can take the values from
0 to 512. Setting this value to 0 chooses a single spinlock
for all GPT L1 table entries. The default value is set to 1
which corresponds to 512MB per bit.

Change-Id: I710d178072894a3ef40daebea701f74d19e8a3d7
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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build: skip toolchain detection for some targets

Most developers run the `clean`, `checkpatch` and other similar targets
without specifying any other additional build options. When combined
with a f

build: skip toolchain detection for some targets

Most developers run the `clean`, `checkpatch` and other similar targets
without specifying any other additional build options. When combined
with a flow where the developer passes `CROSS_COMPILE` or `CC`
explicitly, and where the default-configured tools are not on the PATH,
these targets will warn about unrecognized toolchain tools.

This change is a workaround for this whereby the toolchain makefile is
not expanded unless a target *not* named `*clean`, `check*` `doc` or
`*tool` has been specified.

Change-Id: I2f2a275964b65253df07c2207043217b14f615fe
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(gpt): add support for large GPT mappings

This patch adds support for large GPT mappings using
Contiguous descriptors. The maximum size of supported
contiguous block in MB is defined in RME_GPT_

feat(gpt): add support for large GPT mappings

This patch adds support for large GPT mappings using
Contiguous descriptors. The maximum size of supported
contiguous block in MB is defined in RME_GPT_MAX_BLOCK
build parameter and takes values 0, 2, 32 and 512 and
by default set to 2 in make_helpers/defaults.mk.
Setting RME_GPT_MAX_BLOCK value to 0 disables use of
Contiguous descriptors.
Function gpt_tlbi_by_pa_ll() and its declaration
are removed from lib/aarch64/misc_helpers.S and
include/arch/aarch64/arch_helpers.h, because the
GPT library now uses tlbirpalos_xxx() functions.

Change-Id: Ia9a59bde1741c5666b4ca1de9324e6dfd6f734eb
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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