1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36- ``WORKAROUND_CVE_2024_5660``: Enables mitigation for `CVE-2024-5660`. 37 The fix is to disable hardware page aggregation by setting CPUECTLR_EL1[46] 38 in EL3 FW. This build option should be set to 1 if the target platform contains 39 at least 1 CPU that requires this mitigation. Defaults to 1. 40 41.. _arm_cpu_macros_errata_workarounds: 42 43CPU Errata Workarounds 44---------------------- 45 46TF-A exports a series of build flags which control the errata workarounds that 47are applied to each CPU by the reset handler. The errata details can be found 48in the CPU specific errata documents published by Arm: 49 50- `Cortex-A53 MPCore Software Developers Errata Notice`_ 51- `Cortex-A57 MPCore Software Developers Errata Notice`_ 52- `Cortex-A72 MPCore Software Developers Errata Notice`_ 53 54The errata workarounds are implemented for a particular revision or a set of 55processor revisions. This is checked by the reset handler at runtime. Each 56errata workaround is identified by its ``ID`` as specified in the processor's 57errata notice document. The format of the define used to enable/disable the 58errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 59is for example ``A57`` for the ``Cortex_A57`` CPU. 60 61Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 62write errata workaround functions. 63 64All workarounds are disabled by default. The platform is responsible for 65enabling these workarounds according to its requirement by defining the 66errata workaround build flags in the platform specific makefile. In case 67these workarounds are enabled for the wrong CPU revision then the errata 68workaround is not applied. In the DEBUG build, this is indicated by 69printing a warning to the crash console. 70 71In the current implementation, a platform which has more than 1 variant 72with different revisions of a processor has no runtime mechanism available 73for it to specify which errata workarounds should be enabled or not. 74 75The value of the build flags is 0 by default, that is, disabled. A value of 1 76will enable it. 77 78For Cortex-A9, the following errata build flags are defined : 79 80- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 81 CPU. This needs to be enabled for all revisions of the CPU. 82 83For Cortex-A15, the following errata build flags are defined : 84 85- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 86 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 87 88- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 89 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 90 91For Cortex-A17, the following errata build flags are defined : 92 93- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 94 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 95 96- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 97 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 98 99For Cortex-A35, the following errata build flags are defined : 100 101- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 102 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 103 104For Cortex-A53, the following errata build flags are defined : 105 106- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 107 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 108 109- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 110 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 111 112- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 113 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 114 115- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 116 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 117 118- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 119 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 120 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 121 sections. 122 123- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 124 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 125 r0p4 and onwards, this errata is enabled by default in hardware. Identical to 126 ``A53_DISABLE_NON_TEMPORAL_HINT``. 127 128- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 129 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 130 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 131 which are 4kB aligned. 132 133- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 134 CPUs. Though the erratum is present in every revision of the CPU, 135 this workaround is only applied to CPUs from r0p3 onwards, which feature 136 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 137 Earlier revisions of the CPU have other errata which require the same 138 workaround in software, so they should be covered anyway. 139 140- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 141 revisions of Cortex-A53 CPU. 142 143For Cortex-A55, the following errata build flags are defined : 144 145- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 146 CPU. This needs to be enabled only for revision r0p0 of the CPU. 147 148- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 149 CPU. This needs to be enabled only for revision r0p0 of the CPU. 150 151- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 152 CPU. This needs to be enabled only for revision r0p0 of the CPU. 153 154- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 155 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 156 157- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 158 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 159 160- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 161 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 162 163- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 164 revisions of Cortex-A55 CPU. 165 166For Cortex-A57, the following errata build flags are defined : 167 168- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 169 CPU. This needs to be enabled only for revision r0p0 of the CPU. 170 171- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 172 CPU. This needs to be enabled only for revision r0p0 of the CPU. 173 174- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 175 CPU. This needs to be enabled only for revision r0p0 of the CPU. 176 177- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 178 CPU. This needs to be enabled only for revision r0p0 of the CPU. 179 180- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 181 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 182 183- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 184 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 185 186- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 187 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 188 189- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 190 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 191 192- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 193 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 194 195- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 196 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 197 198- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 199 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 200 201- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 202 revisions of Cortex-A57 CPU. 203 204For Cortex-A72, the following errata build flags are defined : 205 206- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 207 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 208 209- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 210 revisions of Cortex-A72 CPU. 211 212For Cortex-A73, the following errata build flags are defined : 213 214- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 215 CPU. This needs to be enabled only for revision r0p0 of the CPU. 216 217- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 218 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 219 220For Cortex-A75, the following errata build flags are defined : 221 222- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 223 CPU. This needs to be enabled only for revision r0p0 of the CPU. 224 225- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 226 CPU. This needs to be enabled only for revision r0p0 of the CPU. 227 228For Cortex-A76, the following errata build flags are defined : 229 230- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 231 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 232 233- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 234 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 235 236- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 237 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 238 239- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 240 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 241 242- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 243 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 244 245- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 246 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 247 248- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 249 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 250 251- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 252 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 253 254- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 255 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 256 limitation of errata framework this errata is applied to all revisions 257 of Cortex-A76 CPU. 258 259- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 260 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 261 262- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 263 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 264 265- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 266 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 267 still open. 268 269For Cortex-A77, the following errata build flags are defined : 270 271- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 272 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 273 274- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 275 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 276 277- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 278 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 279 280- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 281 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 282 283- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 284 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 285 286 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 287 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 288 289 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 290 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 291 292For Cortex-A78, the following errata build flags are defined : 293 294- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 295 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 296 297- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 298 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 299 300- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 301 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 302 issue but there is no workaround for that revision. 303 304- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 305 CPU. This needs to be enabled for revisions r0p0 and r1p0. 306 307- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 308 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 309 310- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 311 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It 312 is still open. 313 314- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 315 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 316 is present in r0p0 but there is no workaround. It is still open. 317 318- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 319 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 320 it is still open. 321 322- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 323 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 324 it is still open. 325 326- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 327 CPU, this erratum affects system configurations that do not use an ARM 328 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 329 and r1p2 and it is still open. 330 331- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 332 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 333 it is still open. 334 335- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 336 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 337 it is still open. 338 339- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 340 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 341 it is still open. 342 343For Cortex-A78AE, the following errata build flags are defined : 344 345- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 346 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 347 This erratum is still open. 348 349- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 350 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 351 erratum is still open. 352 353- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 354 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 355 This erratum is still open. 356 357- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 358 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 359 erratum is still open. 360 361- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 362 Cortex-A78AE CPU. This erratum affects system configurations that do not use 363 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 364 r0p2. This erratum is still open. 365 366For Cortex-A78C, the following errata build flags are defined : 367 368- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 369 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 370 fixed in r0p1. 371 372- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 373 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 374 fixed in r0p1. 375 376- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to 377 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 378 it is still open. 379 380- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 381 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 382 it is still open. 383 384- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 385 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 386 erratum is still open. 387 388- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 389 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 390 erratum is still open. 391 392- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to 393 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 394 erratum is still open. 395 396- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 397 Cortex-A78C CPU, this erratum affects system configurations that do not use 398 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 399 and is still open. 400 401- ``ERRATA_A78C_2743232`` : This applies erratum 2743232 workaround to 402 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 403 This erratum is still open. 404 405- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 406 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 407 This erratum is still open. 408 409- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 410 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 411 This erratum is still open. 412 413For Cortex-X1 CPU, the following errata build flags are defined: 414 415- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 416 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 417 418- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 419 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 420 421- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 422 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 423 424For Neoverse N1, the following errata build flags are defined : 425 426- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 427 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 428 429- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 430 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 431 432- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 433 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 434 435- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 436 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 437 438- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 439 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 440 441- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 442 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 443 444- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 445 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 446 447- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 448 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 449 450- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 451 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 452 453- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 454 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 455 456- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 457 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 458 459- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 460 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 461 462- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 463 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 464 revisions r0p0, r1p0, and r2p0 there is no workaround. 465 466- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 467 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 468 still open. 469 470For Neoverse V1, the following errata build flags are defined : 471 472- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 473 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 474 r1p0. 475 476- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 477 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 478 in r1p1. 479 480- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 481 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 482 in r1p1. 483 484- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 485 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 486 in r1p1. 487 488- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 489 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 490 491- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 492 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 493 CPU. 494 495- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 496 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 497 issue is present in r0p0 as well but there is no workaround for that 498 revision. It is still open. 499 500- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 501 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 502 CPU. It is still open. 503 504- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 505 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 506 It is still open. 507 508- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 509 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 510 issue is present in r0p0 as well but there is no workaround for that 511 revision. It is still open. 512 513- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 514 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of 515 the CPU. 516 517- ``ERRATA_V1_2348377``: This applies errata 2348377 workaroud to Neoverse-V1 518 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 519 It has been fixed in r1p2. 520 521- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 522 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 523 It is still open. 524 525- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 526 CPU, this erratum affects system configurations that do not use an ARM 527 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 528 It has been fixed in r1p2. 529 530- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 531 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 532 CPU. It is still open. 533 534- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 535 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 536 CPU. It is still open. 537 538- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 539 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 540 CPU. It is still open. 541 542For Neoverse V2, the following errata build flags are defined : 543 544- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2 545 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still 546 open. 547 548- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2 549 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 550 r0p2. 551 552- ``ERRATA_V2_2662553``: This applies errata 2662553 workaround to Neoverse-V2 553 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 554 r0p2. 555 556- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 557 CPU, this affects system configurations that do not use and ARM interconnect 558 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 559 in r0p2. 560 561- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 562 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 563 r0p2. 564 565- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 566 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 567 r0p2. 568 569- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 570 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 571 r0p2. 572 573- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 574 CPU, this affects all configurations. This needs to be enabled for revisions 575 r0p0 and r0p1. It has been fixed in r0p2. 576 577For Cortex-A710, the following errata build flags are defined : 578 579- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 580 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 581 r2p0 of the CPU. It is still open. 582 583- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 584 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 585 r2p0 of the CPU. It is still open. 586 587- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 588 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 589 and is still open. 590 591- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 592 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 593 of the CPU and is still open. 594 595- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 596 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 597 is still open. 598 599- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to 600 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 601 and r2p1 of the CPU and is still open. 602 603- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 604 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 605 of the CPU and is fixed in r2p1. 606 607- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 608 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 609 of the CPU and is fixed in r2p1. 610 611- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 612 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 613 and is fixed in r2p1. 614 615- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 616 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 617 of the CPU and is fixed in r2p1. 618 619- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 620 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 621 r2p1 of the CPU and is still open. 622 623- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 624 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 625 of the CPU and is fixed in r2p1. 626 627- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 628 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 629 of the CPU and is fixed in r2p1. 630 631- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 632 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 633 of the CPU and is fixed in r2p1. 634 635- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 636 CPU, and applies to system configurations that do not use and ARM 637 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 638 is still open. 639 640- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to 641 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 642 r2p1 of the CPU and is still open. 643 644- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 645 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 646 r2p1 of the CPU and is still open. 647 648- ``ERRATA_A710_2778471``: This applies errata 2778471 workaround to Cortex-A710 649 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 650 CPU and is still open. 651 652For Neoverse N2, the following errata build flags are defined : 653 654- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 655 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 656 657- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 658 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 659 660- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 661 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 662 663- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 664 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 665 666- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 667 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 668 669- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 670 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 671 672- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 673 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. 674 675- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 676 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 677 678- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 679 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 680 681- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 682 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 683 684- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 685 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 686 687- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 688 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 689 r0p1. 690 691- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 692 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 693 r0p1. 694 695- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 696 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, 697 it is fixed in r0p3. 698 699- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 700 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 701 702- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 703 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 704 r0p1. 705 706- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 707 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 708 in r0p3. 709 710- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 711 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 712 in r0p3. 713 714- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 715 CPU, this erratum affects system configurations that do not use and ARM 716 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 717 It is fixed in r0p3. 718 719- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 720 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 721 in r0p3. 722 723For Cortex-X2, the following errata build flags are defined : 724 725- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 726 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 727 it is still open. 728 729- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 730 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU, 731 it is still open. 732 733- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 734 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. 735 736- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 737 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 738 CPU, it is fixed in r2p1. 739 740- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 741 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 742 CPU, it is fixed in r2p1. 743 744- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 745 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 746 CPU, it is fixed in r2p1. 747 748- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 749 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 750 in r2p1. 751 752- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 753 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 754 CPU and is still open. 755 756- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 757 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU 758 and is fixed in r2p1. 759 760- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2 761 CPU and affects system configurations that do not use an ARM interconnect IP. 762 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 763 still open. 764 765- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 766 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 767 CPU and is still open. 768 769- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 770 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 771 CPU and is still open. 772 773- ``ERRATA_X2_2778471``: This applies errata 2778471 workaround to Cortex-X2 774 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 775 CPU and it is still open. 776 777For Cortex-X3, the following errata build flags are defined : 778 779- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 780 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of 781 the CPU and is still open. 782 783- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3 784 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it 785 is fixed in r1p1. 786 787- ``ERRATA_X3_2302506``: This applies errata 2302506 workaround to the Cortex-X3 788 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is 789 fixed in r1p2. 790 791- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 792 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 793 of the CPU, it is fixed in r1p1. 794 795- ``ERRATA_X3_2372204``: This applies errata 2372204 workaround to 796 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 797 of the CPU, it is fixed in r1p1. 798 799- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 800 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 801 CPU, it is fixed in r1p2. 802 803- ``ERRATA_X3_2641945``: This applies errata 2641945 workaround to Cortex-X3 804 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU. 805 It is fixed in r1p1. 806 807- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3 808 CPU and affects system configurations that do not use an ARM interconnect 809 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 810 in r1p2. 811 812- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to 813 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 814 r1p1. It is fixed in r1p2. 815 816- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3 817 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is 818 fixed in r1p2. 819 820- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3 821 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 822 CPU. It is fixed in r1p2. 823 824For Cortex-X4, the following errata build flags are defined : 825 826- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4 827 CPU and affects system configurations that do not use an Arm interconnect IP. 828 This needs to be enabled for revisions r0p0 and is fixed in r0p1. 829 The workaround for this erratum is not implemented in EL3, but the flag can 830 be enabled/disabled at the platform level. The flag is used when the errata ABI 831 feature is enabled and can assist the Kernel in the process of 832 mitigation of the erratum. 833 834- ``ERRATA_X4_2726228``: This applies erratum 2726228 workaround to Cortex-X4 835 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in 836 r0p2. 837 838- ``ERRATA_X4_2740089``: This applies errata 2740089 workaround to Cortex-X4 839 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed 840 in r0p2. 841 842- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4 843 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 844 845- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4 846 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 847 848- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 849 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 850 851- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4 852 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 853 854- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4 855 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. 856 857For Cortex-A510, the following errata build flags are defined : 858 859- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to 860 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is 861 fixed in r0p1. 862 863- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 864 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 865 r0p2, r0p3 and r1p0, it is fixed in r1p1. 866 867- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 868 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 869 r0p2, it is fixed in r0p3. 870 871- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 872 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 873 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 874 workaround for those revisions. 875 876- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to 877 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is 878 fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no 879 workaround for those revisions. 880 881- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 882 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 883 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 884 ENABLE_MPMM=1. 885 886- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 887 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 888 r0p3 and r1p0, it is fixed in r1p1. 889 890- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 891 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 892 r0p3 and r1p0, it is fixed in r1p1. 893 894- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 895 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 896 r0p3, r1p0 and r1p1. It is fixed in r1p2. 897 898- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 899 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 900 r0p3, r1p0, r1p1, and is fixed in r1p2. 901 902- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 903 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 904 r0p3, r1p0, r1p1. It is fixed in r1p2. 905 906- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 907 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 908 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 909 910For Cortex-A520, the following errata build flags are defined : 911 912- ``ERRATA_A520_2630792``: This applies errata 2630792 workaround to 913 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the 914 CPU and is still open. 915 916- ``ERRATA_A520_2858100``: This applies errata 2858100 workaround to 917 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 918 It is still open. 919 920- ``ERRATA_A520_2938996``: This applies errata 2938996 workaround to 921 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1. 922 It is fixed in r0p2. 923 924For Cortex-A715, the following errata build flags are defined : 925 926- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to 927 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. 928 It is fixed in r1p1. 929 930- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to 931 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is 932 fixed in r1p1. 933 934- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to 935 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and 936 when SPE(Statistical profiling extension)=True. The errata is fixed 937 in r1p1. 938 939- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to 940 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 941 It is fixed in r1p1. 942 943- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to 944 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no 945 workaround for revision r0p0. It is fixed in r1p1. 946 947- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to 948 Cortex-A715 CPU. This needs to be enabled only for revision r1p0. 949 It is fixed in r1p1. 950 951- ``ERRATA_A715_2728106``: This applies errata 2728106 workaround to 952 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0 953 and r1p1. It is fixed in r1p2. 954 955For Cortex-A720, the following errata build flags are defined : 956 957- ``ERRATA_A720_2792132``: This applies errata 2792132 workaround to 958 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 959 It is fixed in r0p2. 960 961- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to 962 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 963 It is fixed in r0p2. 964 965- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to 966 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 967 It is fixed in r0p2. 968 969- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to 970 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. 971 It is fixed in r0p2. 972 973DSU Errata Workarounds 974---------------------- 975 976Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 977Shared Unit) errata. The DSU errata details can be found in the respective Arm 978documentation: 979 980- `Arm DSU Software Developers Errata Notice`_. 981 982Each erratum is identified by an ``ID``, as defined in the DSU errata notice 983document. Thus, the build flags which enable/disable the errata workarounds 984have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 985of DSU errata workarounds are similar to `CPU errata workarounds`_. 986 987For DSU errata, the following build flags are defined: 988 989- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 990 affected DSU configurations. This errata applies only for those DSUs that 991 revision is r0p0 (on r0p1 it is fixed). However, please note that this 992 workaround results in increased DSU power consumption on idle. 993 994- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 995 affected DSU configurations. This errata applies only for those DSUs that 996 contain the ACP interface **and** the DSU revision is older than r2p0 (on 997 r2p0 it is fixed). However, please note that this workaround results in 998 increased DSU power consumption on idle. 999 1000- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 1001 affected DSU configurations. This errata applies for those DSUs with 1002 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 1003 please note that this workaround results in increased DSU power consumption 1004 on idle. 1005 1006CPU Specific optimizations 1007-------------------------- 1008 1009This section describes some of the optimizations allowed by the CPU micro 1010architecture that can be enabled by the platform as desired. 1011 1012- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 1013 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 1014 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 1015 of the L2 by set/way flushes any dirty lines from the L1 as well. This 1016 is a known safe deviation from the Cortex-A57 TRM defined power down 1017 sequence. Each Cortex-A57 based platform must make its own decision on 1018 whether to use the optimization. 1019 1020- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 1021 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 1022 in a way most programmers expect, and will most probably result in a 1023 significant speed degradation to any code that employs them. The Armv8-A 1024 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 1025 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 1026 flag enforces this behaviour. This needs to be enabled only for revisions 1027 <= r0p3 of the CPU and is enabled by default. 1028 1029- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 1030 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 1031 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 1032 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 1033 `Cortex-A57 Software Optimization Guide`_. 1034 1035- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 1036 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 1037 this bit only if their memory system meets the requirement that cache 1038 line fill requests from the Cortex-A57 processor are atomic. Each 1039 Cortex-A57 based platform must make its own decision on whether to use 1040 the optimization. This flag is disabled by default. 1041 1042- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 1043 level cache(LLC) is present in the system, and that the DataSource field 1044 on the master CHI interface indicates when data is returned from the LLC. 1045 This is used to control how the LL_CACHE* PMU events count. 1046 Default value is 0 (Disabled). 1047 1048GIC Errata Workarounds 1049---------------------- 1050- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 1051 workaround for the affected GIC600 and GIC600-AE implementations. It applies 1052 to implementations of GIC600 and GIC600-AE with revisions less than or equal 1053 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 1054 then this flag is enabled; otherwise, it is 0 (Disabled). 1055 1056-------------- 1057 1058*Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.* 1059 1060.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 1061.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 1062.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 1063.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 1064.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 1065.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 1066.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 1067.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 1068